Datasheet ADRF6520 (Analog Devices) - 10

ADRF6520 Data Sheet 16 1.00 36MHz FILTER 36MHz FILTER 144MHz FILTER 144MHz FILTER 14 720MHz FILTER 0.75 720MHz FILTER BYPASS MODE ) BYPASS MODE dB 12 ( 0.50 H s) n TC ( 10 A 0.25 M AY L IS 8 M 0 DE E D UP 6 –0.25 RO LITU G P M 4 –0.50 I/Q A 2 –0.75 0 –1.00 5 50 500
015
1 10 100 1000
018
FREQUENCY (MHz)
14830-
FREQUENCY (MHz)
14830- Figure 15. Group Delay vs. Frequency for 36 MHz, 144 MHz, Figure 18. IQ Amplitude Mismatch vs. Frequency for 36 MHz, 144 MHz, 720 MHz, and Bypass Mode 720 MHz, and Bypass Mode
300 100 36MHz FILTER BYPASS MODE 250 144MHz FILTER 720MHz FILTER 200 s) s) p p 150 50 CH ( 100 CH ( AT AT M 50 M IS IS M 0 M 0 AY AY L –50 L DE DE –100 UP UP –150 –50 RO RO G G –200 –250 –300 –100 3 13 23 33 43 53 63 73 83 93 103 113 123 133 143 153
016
0 125 250 375 500 625 750 875 1000 1125 1250
119
FREQUENCY (MHz) FREQUENCY (MHz)
14830- 14830- Figure 16. IQ Group Delay Mismatch vs. Frequency for 36 MHz and 144 MHz Figure 19. IQ Group Delay Mismatch vs. Frequency for 720 MHz and Bypass Mode
16 60 440 430 15 55 420 14 50 mA) N ( 410 IO 13 45 T P Bm) B) d d 400 UM 12 40 B ( N ( NS 1d AI 390 P G CO O 11 35 NT 380 10 30 3.15V, 144MHz 3.15V, 720MHz 370 3.3V, 144MHz 3.3V, 720MHz CURRE 3.45V, 144MHz 3.45V, 720MHz 9 25 3.15V, 36MHz 3.15V, BYPASS OP1dB 360 3.3V, 36MHz 3.3V, BYPASS GAIN 3.45V, 36MHz 3.45V, BYPASS 8 20 350 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
317
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80
035
VGN2 (V)
14830-
TEMPERATURE (°C)
14830- Figure 17. OP1dB vs. Gain at a Fundamental of 500 MHz Figure 20. Current Consumption vs. Temperature for 36 MHz, 144 MHz, 720 MHz, and Bypass Mode Rev. 0 | Page 10 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT VGAs RMS DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6520 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS SPI REGISTER AND TIMING REGISTER READ/WRITE TIMING Write Cycle Read Cycle APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING RMS DETECTOR CONNECTIONS VGA2 GAIN STEP RESPONSE LINEAR OPERATION OF THE ADRF6520 EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE