Datasheet AD4110-1 (Analog Devices) - 6

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AD4110-1 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments
RTD EXCITATION CURRENTS14 External reference voltage (VREF) = 2.5 V ± 0% Current Outputs 0.1 to 1 mA Programmable (see Table 30) Initial Error, Internal Reference −0.3 +0.3 % Current ≥ 400 µA, TA = 25°C Resistor −1 +1 % Current = 100 µA, TA = 25°C Initial Drift 130 ppm See Figure 44 and Figure 45 Drift vs. Temperature2 −45 +45 ppm/°C Internal reference resistor (including reference resistor drift) −18 +18 ppm/°C External reference resistor (excluding reference resistor drift) Drift vs. Time5, 15 150 ppm Internal resistor, over 1000 hours 150 ppm External resistor, over 1000 hours Load Regulation2 0.01 %/V Line Regulation2 4 ppm/V Related to VSS and VDD Noise2 See Table 22 and Table 23 TA = 25°C Current Matching15 0.05 % AIN(+) and AIN(−) pins, excludes 100 µA Current Matching Drift 0.0002 %/°C AIN(+) and AIN(−) pins, excludes 100 µA Compliance VDD − 5 V REFERENCE VOLTAGE (INPUT) Reference Voltage Input, V 2, 14 REF 1 2.5 AVDD5 – 1.6 V REFIN(+) − REFIN(−) = VREF RTD mode disabled 2.45 2.5 2.55 V RTD mode enabled VREF Input Current 200 nA VREF+ reference buffer on 100 µA VREF− reference buffer on 36 µA/V VREF+ reference buffer off 75 µA/V VREF− reference buffer off VREF Input Current Drift 1.3 nA/°C VREF+ reference buffer on −3.5 nA/°C VREF− reference buffer on 10 nA/V/°C VREF+ reference buffer off 10 nA/V/°C VREF− reference buffer off Absolute REFIN Voltage Limits AGND − 0.05 AVDD5 + 0.05 V AGND AVDD5 V Reference buffer on Common-Mode Rejection 95 dB REFERENCE VOLTAGE (OUTPUT) Output Voltage 2.5 V REFOUT pin Initial Accuracy2 −0.16 +0.16 V TA = 25°C Temperature Coefficient2 10 50 ppm/°C Long Term Stability5 600 ppm Over 1000 hours Reference Load Current, ILOAD 10 mA Power Supply Rejection 93 dB Load Regulation 75 µV/mA VBIAS Voltage AGND V Output Current Limit ±50 µA Source or sink, depending on the AIN(−) pin potential referenced to AGND OPEN WIRE DETECTION CURRENTS Current Output ±0.71 ±1 ±1.45 µA ±100 µA Compliance VSS + 2 VDD − 2 V Rev. 0 | Page 6 of 74 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SUPPLY SEQUENCE PROTECTION DIODE ANALOG INPUT PULL-UP/PULL-DOWN CURRENTS ANTIALIASING FILTER RTD EXCITATION CURRENTS FIELD POWER SUPPLY MODE NO POWER SUPPLY MODE BIAS VOLTAGE GENERATOR PGA CALIBRATION REGISTERS SERIAL INTERFACE CLOCK ADC ADC FILTER REGISTERS ADC GAIN AND OFFSET REGISTERS NOISE PERFORMANCE AND RESOLUTION MODES OF OPERATION DEFAULT MODE OF OPERATION ON POWER-UP CHANGING THE DEFAULT MODE OF OPERATION FOR FUTURE POWER-UP CYCLES POWER SUPPLY REQUIREMENTS SYSTEM CLOCK REQUIREMENTS BIPOLAR AND UNIPOLAR OUTPUT AUXILIARY LOW VOLTAGE INPUTS DIGITAL FILTER CONTINUOUS CONVERSION MODE INPUT AUTO SEQUENCING SINGLE CONVERSION MODE ADC CONVERSION DELAY BIAS VOLTAGE GENERATOR ANTIALIASING FILTER CIRCUIT CURRENT MODE Transimpedance Gain Using an External Sense Resistor VOLTAGE AND THERMOCOUPLE MODE Input Scaling for Voltage Mode Thermocouple Inputs RTD MODE Generating RTD Currents with an External Resistor Excitation Currents RTD Initial Drift 4-Wire RTD 3-Wire RTD 2-Wire RTD Alternative 3-Wire Configuration FIELD POWER SUPPLY MODE Overvoltage Protection NO POWER SUPPLY MODE Voltage Mode Current Mode System Redundancy GAIN CALIBRATION DATA REGISTER GAIN CALIBRATION IN VOLTAGE MODE GAIN CALIBRATION IN CURRENT MODE SCALING FACTOR AUTOCALIBRATION MODES APPLICATION EXAMPLES Example 1 Example 2 DIAGNOSTICS AND PROTECTION DIAGNOSTIC FLAGS ERROR PIN OVERTEMPERATURE DETECTION AND THERMAL SHUTDOWN OVERVOLTAGE AND UNDERVOLTAGE DETECTION OVERVOLTAGE PROTECTION DIAGNOSING OVERVOLTAGE AND UNDERVOLTAGE CONDITIONS OPEN WIRE DETECTION DIAGNOSTICS FOR RTD MEASUREMENTS AND RTD FLAGS NOISE, SETTLING TIME, AND DIGITAL FILTERING DIGITAL FILTER SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS RTD MODE NOISE PERFORMANCE SERIAL PERIPHERAL INTERFACE RESETTING THE AD4110-1 SPI COMMAND TO COMMUNICATIONS REGISTER DOUT/ PIN WRITE OPERATION READ OPERATION MULTIPLE DEVICES ON THE SPI BUS CRC CHECKSUM CRC CHECKSUM METHODS Polynomial Calculation Polynomial CRC Calculation of a 24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation REGISTER DETAILS AFE REGISTER MAP AFE REGISTER DESCRIPTIONS AFE_TOP_STATUS Register AFE_CNTRL1 Register AFE_CLK_CTRL Register AFE_CNTRL2 Register PGA_RTD_CTRL Register AFE_ERR_DISABLE Register AFE_DETAIL_STATUS Register AFE_CAL_DATA Register AFE_RSENSE_DATA Register NO_PWR_DEFAULT_SEL Register NO_PWR_DEFAULT_STATUS Register ADC REGISTER MAP ADC REGISTER DESCRIPTIONS ADC_STATUS Register ADC_MODE Register ADC_INTERFACE Register ADC_CONFIG Register Data Register Filter Register ADC_GPIO_CONFIG Register ID Register ADC_OFFSET0 Register ADC_OFFSET1 Register ADC_OFFSET2 Register ADC_OFFSET3 Register ADC_GAIN0 Register ADC_GAIN1 Register ADC_GAIN2 Register ADC_GAIN3 Register OUTLINE DIMENSIONS ORDERING GUIDE