Datasheet AD7768-1 (Analog Devices) - 4

AD7768-1 Data Sheet GENERAL DESCRIPTION
The AD7768-1 is a low power, high performance, Σ-Δ analog- The AD7768-1 offers extensive digital filtering capabilities that to-digital converter (ADC), with a Σ-Δ modulator and digital meet a wide range of system requirements. The filter options filter for precision conversion of both ac and dc signals. The allow configuration for frequency domain measurements with AD7768-1 is a single-channel version of the AD7768, an 8-channel, tight gain error over frequency, linear phase response requirements simultaneously sampling, Σ-Δ ADC. The AD7768-1 provides a (brick wal filter), a low latency path (sinc5 or sinc3) for use single configurable and reusable data acquisition (DAQ) footprint, in control loop applications, and measuring dc inputs with the which establishes a new industry standard in combined ac and ability to configure the sinc3 filter to reject the line frequency of dc performance and enables instrumentation and industrial system either 50 Hz or 60 Hz. All filters offer programmable decimation. designers to design across multiple measurement variants for A 1.024 MHz sinc5 filter path exists for users seeking an even both isolated and nonisolated applications. higher ODR than is achievable using the low ripple FIR filter. The AD7768-1 achieves a 108.5 dB dynamic range when using This path is quantization noise limited. Therefore, it is best the low ripple, finite impulse response (FIR) digital filter at suited for customers requiring minimum latency for control 256 kSPS, giving 110.8 kHz input bandwidth, combined with loops or implementing custom digital filtering on an external ±1.1 ppm integral nonlinearity (INL), ±30 µV offset error, and field programmable gate array (FPGA) or digital signal ±30 ppm gain error. processor (DSP). A wider bandwidth, up to 500 kHz Nyquist (filter −3 dB point The filter options include the following: of 204 kHz), is available using the sinc5 filter, enabling a view of • A low ripple FIR filter with a ±0.005 dB pass-band ripple to signals over an extended range. 102.4 kHz. The AD7768-1 offers the user the flexibility to configure and • A low latency sinc5 filter with up to a 1.024 MHz data rate optimize for input bandwidth vs. output data rate (ODR) and vs. to maximize control loop responsiveness. power dissipation. The flexibility of the AD7768-1 allows • A low latency sinc3 filter that is ful y programmable, with dynamic analysis of a changing input signal, making the device 50 Hz/60 Hz rejection capabilities. particularly useful in general-purpose DAQ systems. The selection of one of three available power modes al ows the When using the AD7768-1, embedded analog functionality designer to achieve required noise targets while minimizing within the AD7768-1 greatly reduces the design burden over the power consumption. The design of the AD7768-1 is unique in entire application range. The precharge buffer on each analog that it becomes a reusable and flexible platform for low power input decreases the analog input current compared to dc and high performance ac measurement modules. competing products, simplifying the task of an external amplifier to drive the analog input. The AD7768-1 achieves the optimum balance of dc and ac performance with excellent power efficiency. The following A ful buffer input on the reference reduces the input current, three operating modes al ow the user to trade off the input providing a high impedance input for the external reference bandwidth vs. power budgets: device or in buffering any reference sense resistor scenarios used in ratiometric measurements. • Fast mode offers both a sinc filter with up to 256 kSPS and The device operates with a 5.0 V AVDD1 − AVSS supply, a 2.0 V 52.2 kHz of bandwidth, and 26.4 mW of power consumption, to 5.0 V AVDD2 − AVSS supply, and a 1.8 V to 3.3 V IOVDD − or a FIR filter with up to 256 kSPS, 110.8 kHz of bandwidth DGND supply. and 36.8 mW of power consumption. • Median mode offers a FIR filter with up to 128 kSPS, 55.4 kHz In low power mode, the AVDD1, AVDD2, and IOVDD supplies of bandwidth and 19.7 mW of power consumption. can run from a single 3.0 V rail. • Low power mode offers a FIR filter with up to 32 kSPS, The device requires an external reference. The absolute input 13.85 kHz of bandwidth and 6.75 mW of power consumption. reference (REFIN) voltage range is 1 V to AVDD1 − AVSS. The specified operating temperature range is −40°C to +125°C. The device is housed in a 4 mm × 5 mm, 28-lead LFCSP. Note that, throughout this data sheet, multifunction pins, such as XTAL2/MCLK, are referred to either by the entire pin name or by a single function of the pin, for example, MCLK, when only that function is relevant. Rev. A | Page 4 of 80 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 3 V OPERATION TIMING SPECIFICATIONS 1.8 V TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Power vs. Noise Performance Optimization Example of Power vs. Noise Performance Optimization Configuration A Configuration B NOISE PERFORMANCE AND RESOLUTION CORE CONVERTER ADC Core and Signal Chain Analog Inputs and Precharge Buffering VCM Output Reference Input and Buffering CLOCKING AND CLOCK SELECTION CLKSEL Pin Using the Internal Oscillator DIGITAL FILTERING Sinc5 Filter Sinc3 Filter Programming for 50 Hz, 60 Hz, and 50 Hz and 60 Hz Rejection Low Ripple FIR Filter DECIMATION RATE CONTROL ANTIALIASING FILTERING Modulator Saturation Point Modulator Unprotected Zones Modulator Chopping Frequency GETTING STARTED Method of Configuration—PINB Control Mode or SPI Control Mode Digital Filter Type and Decimation Power Mode POWER SUPPLIES Single-Supply Mode Recommended Power Supply Configuration DEVICE CONFIGURATION METHOD PINB Configuration SPI Control PIN CONTROL MODE OVERVIEW Power Mode Data Output Format Diagnostics and Status Bits Daisy-Chaining—PINB Control Mode Only SPI CONTROL OVERVIEW SPI CONTROL MODE MCLK Source and MCLK Division Power-Down Mode Standby Mode SPI Synchronization Offset Calibration Gain Calibration Reset over SPI Control Interface Resume from Shutdown GPIO and STARTB Functions SPI Mode Diagnostic Features Reference Detection Clock Qualification CRC on SPI Transaction Flags for Detection of Illegal Register Write CRC Checks POR Monitor MCLK Counter Product Identification (ID) Number DIGITAL INTERFACE SPI Reading and Writing SPI Control Interface Error Handling CRC Check on Serial Interface Conversion Read Modes Single-Conversion Read Mode Continuous Read Mode Exiting Continuous Read Mode DATA CONVERSION MODES Continuous Conversion Mode One Shot Conversion Mode Single-Conversion Mode Duty Cycled Conversion Mode SYNCHRONIZATION OF MULTIPLE AD7768-1 DEVICES ADDITIONAL FUNCTIONALITY OF THE AD7768-1 Reset Status Header Diagnostics APPLICATIONS INFORMATION ANALOG INPUT RECOMMENDATIONS Recommended Driver Amplifiers ANTIALIASING FILTER DESIGN CONSIDERATIONS RECOMMENDED INTERFACE Initializing the Recommended Interface Recommended Interface for Reading Data Resynchronization of the Recommended Interface PROGRAMMABLE DIGITAL FILTER Filter Coefficients Upload Sequence Example Filter Upload Filter Upload Verification ELECTROMAGNETIC COMPATIBILITY (EMC) TESTING Radiated Immunity Radiated Emissions Electrical Fast Transients (EFTs) AD7768-1 SUBSYSTEM LAYOUT REGISTER SUMMARY REGISTER DETAILS COMPONENT TYPE REGISTER UNIQUE PRODUCT ID REGISTERS DEVICE GRADE AND REVISION REGISTER USER SCRATCHPAD REGISTER DEVICE VENDOR ID REGISTERS INTERFACE FORMAT CONTROL REGISTER POWER AND CLOCK CONTROL REGISTER ANALOG BUFFER CONTROL REGISTER VCM CONTROL REGISTER CONVERSION SOURCE SELECT AND MODE CONTROL REGISTER DIGITAL FILTER AND DECIMATION CONTROL REGISTER SINC3 DECIMATION RATE (MSB REGISTER) SINC3 DECIMATION RATE (LSB REGISTER) PERIODIC CONVERSION RATE CONTROL REGISTER SYNCHRONIZATION MODES AND RESET TRIGGERING REGISTER GPIO PORT CONTROL REGISTER GPIO OUTPUT CONTROL REGISTER GPIO INPUT READ REGISTER OFFSET CALIBRATION MSB REGISTER OFFSET CALIBRATION MID REGISTER OFFSET CALIBRATION LSB REGISTER GAIN CALIBRATION MSB REGISTER GAIN CALIBRATION MID REGISTER GAIN CALIBRATION LSB REGISTER SPI INTERFACE DIAGNOSTIC CONTROL REGISTER ADC DIAGNOSTIC FEATURE CONTROL REGISTER DIGITAL DIAGNOSTIC FEATURE CONTROL REGISTER CONVERSION RESULT REGISTER DEVICE ERROR FLAGS MASTER REGISTER SPI INTERFACE ERROR REGISTER ADC DIAGNOSTICS OUTPUT REGISTER DIGITAL DIAGNOSTICS OUTPUT REGISTER MCLK DIAGNOSTIC OUTPUT REGISTER COEFFICIENT CONTROL REGISTER COEFFICIENT DATA REGISTER ACCESS KEY REGISTER OUTLINE DIMENSIONS ORDERING GUIDE