Datasheet AD7768-1 (Analog Devices) - 6

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AD7768-1 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
SINAD 1 kHz, −0.25 dBFS, sine input 105 107.5 dB THD 1 kHz, −0.25 dBFS, sine input −120 −112 dB SFDR 1 kHz, −0.25 dBFS, sine input 125 dBc Intermodulation Frequency Input A (fa) = 9.7 kHz, Distortion (IMD) Frequency Input B (fb) = 10.3 kHz Second order −125 dB Third order −125 dB ACCURACY No Missing Codes2 Low ripple FIR, sinc5 decimation > 32 24 Bits INL Endpoint method ±1.1 ±7 ppm of FSR Offset Error Fast mode ±30 ±170 µV Median mode ±30 ±170 µV Low power mode ±20 ±80 µV Offset Error Drift2 Fast mode ±300 nV/°C Median mode ±225 nV/°C Low power mode ±100 nV/°C Gain Error TA = 25°C, reference buffer on ±30 ppm of FSR TA = 25°C, reference buffer off ±30 ±70 ppm of FSR Gain Drift vs. Reference buffer off ±0.25 ±0.6 ppm/°C Temperature2 ANALOG INPUTS Differential Input Voltage Reference voltage (VREF) = REF+ − REF− VREF− VREF+ V Absolute AINx Voltage2 Precharge buffers off, absolute voltage on AVSS − 0.05 AVDD1 + 0.05 V AIN+ or AIN− Analog Input Current Fast mode Unbuffered Differential component ±53 µA/V Common-mode component ±17 µA/V Precharge Buffers On3 −20 µA Input Current Drift2 Fast mode Unbuffered ±12.5 nA/V/°C Precharge Buffer On ±3 nA/°C EXTERNAL REFERENCE REFIN Voltage REFIN = (REF+) − (REF−) 1 AVDD1 − AVSS V Absolute REFIN Voltage Reference unbuffered AVSS − 0.05 AVDD1 + 0.05 V Limits Reference precharge buffer on AVSS AVDD1 V Reference buffer on AVSS AVDD1 V Average REFIN Current Reference unbuffered ±80 µA/V Reference precharge buffer on ±20 µA Reference buffer on ±300 nA Average REFIN Current Reference unbuffered ±1.7 nA/V/°C Drift2 Reference precharge buffer on 125 nA/°C Reference buffer on 4 nA/°C Common-Mode Rejection Up to 10 MHz 100 dB Rev. A | Page 6 of 80 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS 3 V OPERATION TIMING SPECIFICATIONS 1.8 V TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CLOCKING, SAMPLING TREE, AND POWER SCALING Power vs. Noise Performance Optimization Example of Power vs. Noise Performance Optimization Configuration A Configuration B NOISE PERFORMANCE AND RESOLUTION CORE CONVERTER ADC Core and Signal Chain Analog Inputs and Precharge Buffering VCM Output Reference Input and Buffering CLOCKING AND CLOCK SELECTION CLKSEL Pin Using the Internal Oscillator DIGITAL FILTERING Sinc5 Filter Sinc3 Filter Programming for 50 Hz, 60 Hz, and 50 Hz and 60 Hz Rejection Low Ripple FIR Filter DECIMATION RATE CONTROL ANTIALIASING FILTERING Modulator Saturation Point Modulator Unprotected Zones Modulator Chopping Frequency GETTING STARTED Method of Configuration—PINB Control Mode or SPI Control Mode Digital Filter Type and Decimation Power Mode POWER SUPPLIES Single-Supply Mode Recommended Power Supply Configuration DEVICE CONFIGURATION METHOD PINB Configuration SPI Control PIN CONTROL MODE OVERVIEW Power Mode Data Output Format Diagnostics and Status Bits Daisy-Chaining—PINB Control Mode Only SPI CONTROL OVERVIEW SPI CONTROL MODE MCLK Source and MCLK Division Power-Down Mode Standby Mode SPI Synchronization Offset Calibration Gain Calibration Reset over SPI Control Interface Resume from Shutdown GPIO and STARTB Functions SPI Mode Diagnostic Features Reference Detection Clock Qualification CRC on SPI Transaction Flags for Detection of Illegal Register Write CRC Checks POR Monitor MCLK Counter Product Identification (ID) Number DIGITAL INTERFACE SPI Reading and Writing SPI Control Interface Error Handling CRC Check on Serial Interface Conversion Read Modes Single-Conversion Read Mode Continuous Read Mode Exiting Continuous Read Mode DATA CONVERSION MODES Continuous Conversion Mode One Shot Conversion Mode Single-Conversion Mode Duty Cycled Conversion Mode SYNCHRONIZATION OF MULTIPLE AD7768-1 DEVICES ADDITIONAL FUNCTIONALITY OF THE AD7768-1 Reset Status Header Diagnostics APPLICATIONS INFORMATION ANALOG INPUT RECOMMENDATIONS Recommended Driver Amplifiers ANTIALIASING FILTER DESIGN CONSIDERATIONS RECOMMENDED INTERFACE Initializing the Recommended Interface Recommended Interface for Reading Data Resynchronization of the Recommended Interface PROGRAMMABLE DIGITAL FILTER Filter Coefficients Upload Sequence Example Filter Upload Filter Upload Verification ELECTROMAGNETIC COMPATIBILITY (EMC) TESTING Radiated Immunity Radiated Emissions Electrical Fast Transients (EFTs) AD7768-1 SUBSYSTEM LAYOUT REGISTER SUMMARY REGISTER DETAILS COMPONENT TYPE REGISTER UNIQUE PRODUCT ID REGISTERS DEVICE GRADE AND REVISION REGISTER USER SCRATCHPAD REGISTER DEVICE VENDOR ID REGISTERS INTERFACE FORMAT CONTROL REGISTER POWER AND CLOCK CONTROL REGISTER ANALOG BUFFER CONTROL REGISTER VCM CONTROL REGISTER CONVERSION SOURCE SELECT AND MODE CONTROL REGISTER DIGITAL FILTER AND DECIMATION CONTROL REGISTER SINC3 DECIMATION RATE (MSB REGISTER) SINC3 DECIMATION RATE (LSB REGISTER) PERIODIC CONVERSION RATE CONTROL REGISTER SYNCHRONIZATION MODES AND RESET TRIGGERING REGISTER GPIO PORT CONTROL REGISTER GPIO OUTPUT CONTROL REGISTER GPIO INPUT READ REGISTER OFFSET CALIBRATION MSB REGISTER OFFSET CALIBRATION MID REGISTER OFFSET CALIBRATION LSB REGISTER GAIN CALIBRATION MSB REGISTER GAIN CALIBRATION MID REGISTER GAIN CALIBRATION LSB REGISTER SPI INTERFACE DIAGNOSTIC CONTROL REGISTER ADC DIAGNOSTIC FEATURE CONTROL REGISTER DIGITAL DIAGNOSTIC FEATURE CONTROL REGISTER CONVERSION RESULT REGISTER DEVICE ERROR FLAGS MASTER REGISTER SPI INTERFACE ERROR REGISTER ADC DIAGNOSTICS OUTPUT REGISTER DIGITAL DIAGNOSTICS OUTPUT REGISTER MCLK DIAGNOSTIC OUTPUT REGISTER COEFFICIENT CONTROL REGISTER COEFFICIENT DATA REGISTER ACCESS KEY REGISTER OUTLINE DIMENSIONS ORDERING GUIDE