Datasheet AD4002, AD4006, AD4010 (Analog Devices)

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18-Bit, 2 MSPS/1 MSPS/500 kSPS, Precision, Pseudo Differential, SAR ADCs Data Sheet AD4002/ AD4006/ AD4010 FEATURES
analog-to-digital converters (ADCs). The AD4002, AD4006,
Throughput: 2 MSPS/1 MSPS/500 kSPS options
and AD4010 offer 2 MSPS, 1 MSPS, and 500 kSPS throughputs,
INL: ±3.2 LSB maximum
respectively. They incorporate ease of use features that reduce
Guaranteed 18-bit, no missing codes
signal chain power consumption, reduce signal chain complexity,
Low power: 70 µW at 10 kSPS, 14 mW at 2 MSPS (total)
and enable higher channel density. The high-Z mode, coupled with
9.75 mW at 2 MSPS, 4.9 mW at 1 MSPS, 2.5 mW at 500 kSPS
a long acquisition phase, eliminates the need for a dedicated high
(VDD only)
power, high speed ADC driver, thus broadening the range of
SNR: 95 dB typical at 1 kHz, VREF = 5 V; 95 dB typical at 100 kHz
low power precision amplifiers that can drive these ADCs directly
THD: −125 dB typical at 1 kHz, VREF = 5 V; −108 dB typical at
while still achieving optimum performance. The input span com-
100 kHz
pression feature enables the ADC driver amplifier and the ADC
Ease of use features reduce system power and complexity
to operate off common supply rails without the need for a negative
Input overvoltage clamp circuit
supply while preserving the ful ADC code range. The low serial
Reduced nonlinear input charge kickback
peripheral interface (SPI) clock rate requirement reduces the digital
High-Z mode
input/output power consumption, broadens processor options,
Long acquisition phase
and simplifies the task of sending data across digital isolation.
Input span compression
Operating from a 1.8 V supply, the AD4002/AD4006/AD4010
Fast conversion time allows low SPI clock rates
sample an analog input (IN+) from 0 V to VREF with respect to a
SPI-programmable modes, read/write capability, status word
ground sense (IN−) with VREF ranging from 2.4 V to 5.1 V. The
Pseudo differential (single-ended) analog input range
AD4002 consumes only 14 mW at 2 MSPS with a minimum SCK
0 V to VREF with VREF from 2.4 V to 5.1 V
rate of 75 MHz in turbo mode; the AD4006 consumes only 7 mW
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
at 1 MSPS; and the AD4010 consumes only 3.5 mW at 500 kSPS.
SAR architecture: no latency/pipeline delay, valid first conversion
The AD4002/AD4006/AD4010 all achieve ±3.2 LSB integral
First conversion accurate
nonlinearity error (INL) maximum, no missing codes at 18 bits,
Guaranteed operation: −40°C to +125°C
and 95 dB signal-to-noise ratio (SNR) for an input frequency (f
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
IN) of 1 kHz. The reference voltage is applied externally and can be
Ability to daisy-chain multiple ADCs and busy indicator
set independently of the supply voltage.
10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP APPLICATIONS
The SPI-compatible versatile serial interface features seven different modes including the ability, using the SDI input, to daisy-chain
Automatic test equipment Machine automation
several ADCs on a single 3-wire bus, and provides an optional
Medical equipment
busy indicator. The AD4002/AD4006/AD4010 are compatible
Battery-powered equipment
with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply.
Precision data acquisition systems
The AD4002/AD4006 are available in a 10-lead MSOP and
GENERAL DESCRIPTION
10-lead LFCSP, and the AD4010 is available in a 10-lead LFCSP, with operation specified from −40°C to +125°C. The devices are The AD4002/AD4006/AD4010 are low noise, low power, high pin compatible with the 18-bit, 2 MSPS AD4003 (see Table 8). speed, 18-bit, precision successive approximation register (SAR)
FUNCTIONAL BLOCK DIAGRAM 2.4V TO 5.1V 1.8V 10µF REF VDD AD4002/ VIO VREF AD4006/ 1.8V TO 5V HIGH-Z V TURBO SDI REF/2 AD4010 MODE MODE 0 IN+ SCK 18-BIT SERIAL 3-WIRE OR 4-WIRE SDO SAR ADC INTERFACE SPI INTERFACE IN– (DAISY CHAIN, CS) STATUS CNV CLAMP SPAN COMPRESSION BITS
001
GND
16233- Figure 1.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION TRANSFER FUNCTIONS APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS ANALOG INPUTS Input Overvoltage Clamp Circuit Switched Capacitor Input RC Filter Values DRIVER AMPLIFIER CHOICE High Frequency Input Signals Multiplexed Applications EASE OF DRIVE FEATURES Input Span Compression High-Z Mode Long Acquisition Phase VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE REGISTER READ/WRITE FUNCTIONALITY STATUS WORD CSB MODE, 3-WIRE TURBO MODE CSB MODE, 3-WIRE WITHOUT BUSY INDICATOR CSB MODE, 3-WIRE WITH BUSY INDICATOR CSB MODE, 4-WIRE TURBO MODE CSB MODE, 4-WIRE WITHOUT BUSY INDICATOR CSB MODE, 4-WIRE WITH BUSY INDICATOR DAISY-CHAIN MODE LAYOUT GUIDELINES EVALUATING THE AD4002/AD4006/AD4010 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE