Datasheet AD4003-KGD (Analog Devices) - 8

AD4003-KGD Known Good Die PIN CONFIGURATION AND FUNCTION DESCRIPTION REF VIO REF VIO VDD VDD ADD4003-KGD TOP VIEW IN+ (Not to Scale) SDI IN– SCK GND GND GND SDO CNV
3 0 -0
TOP VIEW
525 16 Figure 3. Pad Configuration
Table 6. Pad Function Descriptions Pad X-Axis Y-Axis No. (μm) (μm) Mnemonic Description
1 −747.675 +996.855 REF Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be decoupled closely to the GND pin with a 10 μF X7R ceramic capacitor. 2 −747.675 +823.805 REF Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be decoupled closely to the GND pin with a 10 μF X7R ceramic capacitor. 3 −750 +607.545 VDD 1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor. 4 −750 +442.715 VDD 1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 μF ceramic capacitor. 5 −744.365 +272.19 IN+ Differential Positive Analog Input. 6 −744.365 −260.63 IN− Differential Negative Analog Input. 7 −745.845 −382.055 GND Power Supply Ground. 8 −745.845 −546.885 GND Power Supply Ground. 9 −745.845 −702.35 GND Power Supply Ground. 10 +747.78 −942.43 CNV Convert Input. This input has multiple functions. On its leading edge, this input initiates the conversions and selects the interface mode of the device: daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high. 11 +747.78 −733.54 SDO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 12 +747.78 −345.685 SCK Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. 13 +747.78 −132.405 SDI Serial Data Input. This input provides multiple features. This input selects the interface mode of the ADC as follows: daisy-chain mode is selected if SDI is low during the CNV rising edge. In daisy-chain mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. With CNV low, the device can be programmed by clocking in a 16-bit word on SDI on the rising edge of SCK. 14 +747.675 +832.805 VIO Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor. 15 +747.675 +996.855 VIO Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor. Rev. 0 | Page 8 of 9 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Description Outline Dimensions Die Specifications and Assembly Recommendations Ordering Guide