Datasheet AD7980-EP (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 1 MSPS, PulSAR ADC in MSOP/LFCSP |
| 页数 / 页 | 12 / 7 — Enhanced Product. AD7980-EP. PIN CONFIGURATIONS AND FUNCTION … |
| 修订版 | A |
| 文件格式/大小 | PDF / 340 Kb |
| 文件语言 | 英语 |
Enhanced Product. AD7980-EP. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. REF. 10 VIO. VDD. SDI. IN+. TOP VIEW. SCK. (Not to Scale). IN–. SDO
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文件文字版本
Enhanced Product AD7980-EP PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 10 VIO VDD 2 9 SDI AD7980-EP IN+ 3 8 TOP VIEW SCK (Not to Scale) IN– 4 7 SDO
004
GND 5 6 CNV
09304- Figure 4. 10-Lead MSOP Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1 REF AI Reference Input Voltage. The REF range is from 2.4 V to 5.1 V. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 µF capacitor. 2 VDD P Power Supply. 3 IN+ AI Analog Input. It is referred to IN−. The voltage range, for example, the difference between IN+ and IN−, is 0 V to VREF. 4 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows. Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low; if SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. A | Page 7 of 12 Document Outline FEATURES APPLICATIONS APPLICATION DIAGRAM EXAMPLE GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE
004
GND 5 6 CNV
09304- Figure 4. 10-Lead MSOP Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1 REF AI Reference Input Voltage. The REF range is from 2.4 V to 5.1 V. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 µF capacitor. 2 VDD P Power Supply. 3 IN+ AI Analog Input. It is referred to IN−. The voltage range, for example, the difference between IN+ and IN−, is 0 V to VREF. 4 IN− AI Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground. 5 GND P Power Supply Ground. 6 CNV DI Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part, chain, or CS mode. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. 7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. 8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. 9 SDI DI Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows. Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low; if SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. 10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). 1AI = analog input, DI = digital input, DO = digital output, and P = power. Rev. A | Page 7 of 12 Document Outline FEATURES APPLICATIONS APPLICATION DIAGRAM EXAMPLE GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE