Datasheet AD7466-KGD (Analog Devices) - 3
| 制造商 | Analog Devices |
| 描述 | 1.6 V Micro-Power 12-Bit ADC |
| 页数 / 页 | 9 / 3 — Known Good Die. AD7466-KGD. SPECIFICATIONS. Table 1. Parameter. Min. Typ. … |
| 修订版 | A |
| 文件格式/大小 | PDF / 177 Kb |
| 文件语言 | 英语 |
Known Good Die. AD7466-KGD. SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments
该数据表的模型线
文件文字版本
Known Good Die AD7466-KGD SPECIFICATIONS
VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted. TA = TMIN to TMAX, unless otherwise noted. The temperature range for the AD7466-KGD version is −40°C to +85°C.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 30 kHz sine wave Signal-to-Noise and Distortion (SINAD) 69 dB 1.8 V ≤ VDD ≤ 2 V 70 dB 2.5 V ≤ VDD ≤ 3.6 V 70 dB VDD = 1.6 V Signal-to-Noise Ratio (SNR) 70 dB 1.8 V ≤ VDD ≤ 2 V 71 dB 1.8 V ≤ VDD ≤ 2 V 71 dB 2.5 V ≤ VDD ≤ 3.6 V 70.5 dB VDD = 1.6 V Total Harmonic Distortion (THD) −83 dB Peak Harmonic or Spurious Noise (SFDR) −85 dB Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz Second-Order Terms −84 dB Third-Order Terms −86 dB Aperture Delay 10 ns Aperture Jitter 40 ps Full Power Bandwidth 3.2 MHz At 3 dB, 2.5 V ≤ VDD ≤ 3.6 V 1.9 MHz At 3 dB, 1.6 V ≤ VDD ≤ 2.2 V 750 kHz At 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V 450 kHz At 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V DC ACCURACY Maximum specifications apply as typical figures when VDD = 1.6 V Resolution 12 Bits Integral Nonlinearity ±1.5 LSB Differential Nonlinearity −0.9/+1.5 LSB Guaranteed no missed codes to 12 bits Offset Error ±1 LSB Gain Error ±1 LSB Total Unadjusted Error (TUE) ±2 LSB ANALOG INPUT Input Voltage Range 0 VDD V DC Leakage Current ±1 µA Input Capacitance 20 pF LOGIC INPUTS Input High Voltage, VINH 0.7 × VDD V 1.6 V ≤ VDD < 2.7 V 2 V 2.7 V ≤ VDD ≤ 3.6 V Input Low Voltage, VINL 0.2 × VDD V 1.6 V ≤ VDD < 1.8 V 0.3 × VDD V 1.8 V ≤ VDD < 2.7 V 0.8 V 2.7 V ≤ VDD ≤ 3.6 V Input Current, IIN, SCLK Pin ±1 µA Typically 20 nA, VIN = 0 V or VDD Input Current, IIN, CS Pin ±1 µA Input Capacitance, CIN 10 pF Sample tested at 25°C to ensure compliance LOGIC OUTPUTS Output High Voltage, VOH VDD − 0.2 V ISOURCE = 200 µA, VDD = 1.6 V to 3.6 V Output Low Voltage, VOL 0.2 V ISINK = 200 µA Floating-State Leakage Current ±1 µA Floating-State Output Capacitance 10 pF Output Coding Straight (natural) binary Rev. A | Page 3 of 9 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE
VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted. TA = TMIN to TMAX, unless otherwise noted. The temperature range for the AD7466-KGD version is −40°C to +85°C.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE fIN = 30 kHz sine wave Signal-to-Noise and Distortion (SINAD) 69 dB 1.8 V ≤ VDD ≤ 2 V 70 dB 2.5 V ≤ VDD ≤ 3.6 V 70 dB VDD = 1.6 V Signal-to-Noise Ratio (SNR) 70 dB 1.8 V ≤ VDD ≤ 2 V 71 dB 1.8 V ≤ VDD ≤ 2 V 71 dB 2.5 V ≤ VDD ≤ 3.6 V 70.5 dB VDD = 1.6 V Total Harmonic Distortion (THD) −83 dB Peak Harmonic or Spurious Noise (SFDR) −85 dB Intermodulation Distortion (IMD) fa = 29.1 kHz, fb = 29.9 kHz Second-Order Terms −84 dB Third-Order Terms −86 dB Aperture Delay 10 ns Aperture Jitter 40 ps Full Power Bandwidth 3.2 MHz At 3 dB, 2.5 V ≤ VDD ≤ 3.6 V 1.9 MHz At 3 dB, 1.6 V ≤ VDD ≤ 2.2 V 750 kHz At 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V 450 kHz At 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V DC ACCURACY Maximum specifications apply as typical figures when VDD = 1.6 V Resolution 12 Bits Integral Nonlinearity ±1.5 LSB Differential Nonlinearity −0.9/+1.5 LSB Guaranteed no missed codes to 12 bits Offset Error ±1 LSB Gain Error ±1 LSB Total Unadjusted Error (TUE) ±2 LSB ANALOG INPUT Input Voltage Range 0 VDD V DC Leakage Current ±1 µA Input Capacitance 20 pF LOGIC INPUTS Input High Voltage, VINH 0.7 × VDD V 1.6 V ≤ VDD < 2.7 V 2 V 2.7 V ≤ VDD ≤ 3.6 V Input Low Voltage, VINL 0.2 × VDD V 1.6 V ≤ VDD < 1.8 V 0.3 × VDD V 1.8 V ≤ VDD < 2.7 V 0.8 V 2.7 V ≤ VDD ≤ 3.6 V Input Current, IIN, SCLK Pin ±1 µA Typically 20 nA, VIN = 0 V or VDD Input Current, IIN, CS Pin ±1 µA Input Capacitance, CIN 10 pF Sample tested at 25°C to ensure compliance LOGIC OUTPUTS Output High Voltage, VOH VDD − 0.2 V ISOURCE = 200 µA, VDD = 1.6 V to 3.6 V Output Low Voltage, VOL 0.2 V ISINK = 200 µA Floating-State Leakage Current ±1 µA Floating-State Output Capacitance 10 pF Output Coding Straight (natural) binary Rev. A | Page 3 of 9 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE