Datasheet AD7476-EP (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | 1MSPS, 12-Bit ADC in 6 Lead SOT-23 |
| 页数 / 页 | 12 / 5 — AD7476-EP. TIMING SPECIFICATIONS. Table 2. Limit at T. MIN, TMAX. … |
| 文件格式/大小 | PDF / 182 Kb |
| 文件语言 | 英语 |
AD7476-EP. TIMING SPECIFICATIONS. Table 2. Limit at T. MIN, TMAX. Parameter. 3 V. 5 V. Unit. Description. 200µA. IOL. TO OUTPUT. 1.6V. PIN. 50pF. IOH
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AD7476-EP TIMING SPECIFICATIONS
VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Limit at T 1 MIN, TMAX Parameter 2 3 V 5 V Unit Description
f 3 SCLK 10 10 kHz min 12 12 MHz max tCONVERT 16 × tSCLK 16 × tSCLK tQUIET 50 50 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 10 10 ns min Minimum CS pulse width t2 10 10 ns min CS to SCLK setup time t 4 3 20 20 ns max Delay from CS until SDATA three-state disabled t 4 4 40 20 ns max Data access time after SCLK falling edge, A version 70 20 ns max Data access time after SCLK falling edge, B version t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 10 10 ns min SCLK to data valid hold time t 5 8 10 10 ns min SCLK falling edge to SDATA high impedance 25 25 ns max SCLK falling edge to SDATA high impedance tPOWER-UP 1 1 μs typ Power-up time from full power-down 1 3 V specifications apply from VDD = 2.35 V to 3.6 V; 5 V specifications apply from VDD = 4.75 V to 5.25 V. 2 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 3 Mark/space ratio for the SCLK input is 40/60 to 60/40. 4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 5 t8 is derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, is the true bus relinquish time of the part and is independent of the bus loading.
200µA IOL TO OUTPUT 1.6V PIN CL 50pF
-002
200µA IOH
224 09 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. 0 | Page 5 of 12 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE
AD7476-EP TIMING SPECIFICATIONS
VDD = 2.35 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Limit at T 1 MIN, TMAX Parameter 2 3 V 5 V Unit Description
f 3 SCLK 10 10 kHz min 12 12 MHz max tCONVERT 16 × tSCLK 16 × tSCLK tQUIET 50 50 ns min Minimum quiet time required between bus relinquish and start of next conversion t1 10 10 ns min Minimum CS pulse width t2 10 10 ns min CS to SCLK setup time t 4 3 20 20 ns max Delay from CS until SDATA three-state disabled t 4 4 40 20 ns max Data access time after SCLK falling edge, A version 70 20 ns max Data access time after SCLK falling edge, B version t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulse width t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulse width t7 10 10 ns min SCLK to data valid hold time t 5 8 10 10 ns min SCLK falling edge to SDATA high impedance 25 25 ns max SCLK falling edge to SDATA high impedance tPOWER-UP 1 1 μs typ Power-up time from full power-down 1 3 V specifications apply from VDD = 2.35 V to 3.6 V; 5 V specifications apply from VDD = 4.75 V to 5.25 V. 2 Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 3 Mark/space ratio for the SCLK input is 40/60 to 60/40. 4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V. 5 t8 is derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, is the true bus relinquish time of the part and is independent of the bus loading.
200µA IOL TO OUTPUT 1.6V PIN CL 50pF
-002
200µA IOH
224 09 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. 0 | Page 5 of 12 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE