Datasheet AD9213 (Analog Devices) - 4

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AD9213 Preliminary Technical Data Test Conditions/ AD9213-6G AD9213-10G Parameter Comments Temperature1 Min Typ Max Min Typ Max Unit
IVDD_NVG 70°C 363 420 mA IRVDD2 70°C 35 37 mA ISVDD2 + IJVDD2 70°C 29 29 mA I 4 DVDD +IAVDDFS8 70°C 676 1170 mA IJVDD + IJVTT 70°C 490 800 mA ITMU_AVDD2 70°C 2 2 mA ITMU_DVDD1 70°C 3 3 mA Power Dissipation5 70°C 3.7 5.1 W Power-Down Dissipation mW 1 Full temperature range is −10°C to +115°C junction temperature (Tj). Startup at a junction temperature of −40°C is guaranteed.All temperatures are junction temperatures. 2 Sink current if supplied by an external source. This current is normally provided by VNEG_OUT when VNEG_OUT is connected to BVNN1 and AVNN1 on the board. 3 Internally supplied. 4 Digital downconverter (DDC) off. 5 Power with optional PLL off, DDC off. Power and supply currents are estimates.
AC SPECIFICATIONS
Nominal supply voltages, specified maximum sampling rate, internal reference, AIN = −1.0 dBFS.
Table 2. Test Conditions/ AD9213-6G AD9213-10G Parameter Comments Temperature1 Min Typ Max Min Typ Max Unit
ANALOG INPUT Full scale Full 1.4 1.4 V p-p NOISE DENSITY 70°C dBFS/Hz SIGNAL-TO-NOISE RATIO (SNR) fIN = 150 MHz 70°C 58.2 56.0 dBFS fIN = 1000 MHz 70°C 57.0 55.1 dBFS fIN = 2600 MHz 70°C 52.5 50.4 dBFS fIN = 4000 MHz 70°C 49.9 49.5 dBFS SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 150 MHz 70°C 58.1 55.9 dBFS fIN = 1000 MHz 70°C 56.9 55.0 dBFS fIN = 2600 MHz 70°C 52.2 50.1 dBFS fIN = 4000 MHz 70°C 48.6 48.8 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 150 MHz 70°C 9.4 9.0 Bits fIN = 1000 MHz 70°C 9.2 8.8 Bits fIN = 2600 MHz 70°C 8.4 8.0 Bits fIN = 4000 MHz 70°C 7.8 7.8 Bits SPURIOUS FREE DYNAMIC RANGE (SFDR) Including second or third harmonic fIN = 150 MHz 70°C 78 73 dBFS fIN = 1000 MHz 70°C 71 71 dBFS fIN = 2600 MHz 70°C 72 66 dBFS fIN = 4000 MHz 70°C 55 58 dBFS SECOND HARMONIC (H2) fIN = 150 MHz 70°C −79 −75 dBFS fIN = 1000 MHz 70°C −77 −73 dBFS fIN = 2600 MHz 70°C −74 −66 dBFS fIN = 4000 MHz 70°C −55 −58 dBFS Rev. PrG | Page 4 of 97 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9213-6G AD9213-10G EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Input Overvoltage Clamp VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Synthesis Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode and Sensor TMU ADC FAST DETECT FAST THRESHOLD DETECTION (FD) DIGITAL DOWNCONVERTER DDC GENERAL DESCRIPTION Frequency Translation Stage (Optional) Filtering Stage Gain Stage (Optional) Complex to Real Conversion Stage (Optional) DDC FREQUENCY TRANSLATION Variable IF Mode ZIF Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode Example Calculation NCO FTW/POW/MAW/MAB Coherent Mode Example Calculation NCO Channel Selection GPIO Level Control Mode GPIO Edge Control Mode Profile Select Timer Mode Register Map Mode Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization NCO Multichip Synchronization at Startup NCO Multichip Synchronization during Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS M2_HB7 Filter Description M2_HB6 Filter Description M2_HB5 Filter Description M2_HB4 Filter Description M2_HB3 Filter Description M2_HB2 Filter Description M2_HB1 Filter Description M1_TB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop SETTING UP THE AD9213 DIGITAL INTERFACE JESD204B Transport Layer Settings Serial Line Rates K Settings DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION SAMPLED SYSREF MODE AVERAGED SYSREF MODE TEST MODES JESD204B TEST MODES SERIAL PORT INTERFACE MEMORY MAP READING THE MEMORY MAP REGISTER TABLES Open and Reserved Locations Default Values Logic Levels SPI Soft Reset REGISTER DETAILS: SYSTEM CONTROL SIGNALS (SPI_ONLY_REGMAP) REGISTER DETAILS: (USER_CTRL) REGISTER DETAILS: (AD9213_CUST_SPI_REGMAP) REGISTER DETAILS: (MAIN_REGMAP) REGISTER DETAILS: JTX_QBF REGISTER REGISTER DETAILS: DIG_DP_REGMAP REGISTER DETAILS: (AD9213_CUST_REG) REGISTER DETAILS: LCPLL_28NM REGISTER REGISTER DETAILS: JESD204B REGISTER MAP FOR FOUR CHANNELS (JTX_28NM_16CH) APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS