Datasheet AD9690 (Analog Devices)

14-Bit, 1 GSPS/500 MSPS JESD204B, Analog-to-Digital Converter Data Sheet AD9690 FEATURES FUNCTIONAL BLOCK DIAGRAM JESD204B (Subclass 1) coded serial digital outputs AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V) 2.0 W total power at 1 GSPS (default settings) 1.5 W total power at 500 MSPS (default settings) SFDR = 85 dBFS at 340 MHz, 80 dBFS at 985 MHz + ER SNR = 65.3 dBFS at 340 MHz (A IZ IN = −1.0 dBFS), BUFFER L 60.5 dBFS at 985 MHz VIN+ 14 IA TS ADC U 4 SERDOUT0± VIN– CORE TP SERDOUT1± ENOB = 10.8 bits at 10 MHz DDC D204B SER SERDOUT2± S OU SERDOUT3± DNL = ±0.5 LSB JE T CT Tx FD E AS T SPEED INL = ±2.5 LSB F H DE IG Noise density = −154 dBFS/Hz at 1 GSPS H CONTROL 1.25 V, 2.5 V, and 3.3 V dc supply operation REGISTERS V_1P0 FAST No missing codes DETECT Internal ADC voltage reference SYNCINB± JESD204B CLOCK SUBCLASS 1 GENERATION Flexible input range CONTROL SYSREF± CLK+ AD9690-1000: 1. 46 V p-p to 1.94 V p-p (1.70 V p-p nominal) CLK– ÷2 AD9690-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) SPI CONTROL ÷4 PDWN/ STBY Programmable termination impedance ÷8 AD9690
001
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential AGND DRGND DGND SDIO SCLK CSB
12834-
2 GHz usable analog input full power bandwidth
Figure 1.
Amplitude detect bits for efficient AGC implementation 2 integrated wideband digital processors PRODUCT HIGHLIGHTS 12-bit NCO, up to 4 cascaded half-band filters
1. Wide ful power bandwidth supports IF sampling of signals
Differential clock input
up to 2 GHz.
Integer clock divide by 1, 2, 4, or 8
2. Buffered inputs with programmable input termination eases
Flexible JESD204B lane configurations
filter design and implementation.
Small signal dither
3. Two integrated wideband decimation filters and numerical y
APPLICATIONS
controlled oscillator (NCO) blocks supporting multiband receivers.
Communications
4. Flexible serial port interface (SPI) controls various product
Multiband, multimode digital receivers
features and functions to meet specific system requirements.
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
5. Programmable fast overrange detection.
General-purpose software radios
6. 9 mm × 9 mm, 64-lead LFCSP.
Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers Wideband digital predistortion Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9690-1000 AD9690-500 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing Voltage Reference Clock Input Considerations Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC Overrange and Fast Detect ADC Overrange Fast Threshold Detection (FD) Signal Monitor SPORT Over JESD204B Digital Downconverter (DDC) DDC I/Q Input Selection DDC I/Q Output Selection DDC General Description Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Plus Mixer Loss and SFDR Numerically Controlled Oscillator Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR Filters General Description Half-Band Filters HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC Gain Stage DDC Complex—Real Conversion DDC Example Configurations Digital Outputs Introduction to the JESD204B Interface JESD204B Overview Functional Overview Transport Layer Data Link Layer Physical Layer JESD204B Link Establishment Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder Physical Layer (Driver) Outputs Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B Tx Converter Mapping Configuring the JESD204B Link Multichip Synchronization SYSREF± Setup/Hold Window Monitor Test Modes ADC Test Modes JESD204B Block Test Modes Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes Serial Port Interface Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels SPI Soft Reset Memory Map Register Table Applications Information Power Supply Recommendations Exposed Pad Thermal Heat Slug Recommendations AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) Outline Dimensions Ordering Guide