Datasheet AD9234 (Analog Devices) - 9

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Data Sheet AD9234 SWITCHING SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted.
Table 4. AD9234-500 AD9234-1000 Parameter Temperature Min Typ Max Min Typ Max Unit
CLOCK Clock Rate (at CLK+/CLK− Pins) Full 0.3 4 0.3 4 GHz Maximum Sample Rate1 Full 500 1000 MSPS Minimum Sample Rate2 Full 300 300 MSPS Clock Pulse Width High Full 1000 500 ps Clock Pulse Width Low Full 1000 500 ps OUTPUT PARAMETERS Unit Interval (UI)3 Full 80 200 80 100 ps Rise Time (tR) (20% to 80% into 100 Ω Load) 25°C 24 32 24 32 ps Fall Time (tF) (20% to 80% into 100 Ω Load) 25°C 24 32 24 32 ps PLL Lock Time 25°C 2 2 ms Data Rate per Channel (NRZ)4 25°C 3.125 5 12.5 3.125 10 12.5 Gbps LATENCY5 Pipeline Latency Full 55 55 Clock cycles Fast Detect Latency Full 28 28 Clock cycles Wake-Up Time6 Standby 25°C 1 1 ms Power-Down 25°C 4 4 ms APERTURE Aperture Delay (tA) Full 530 530 ps Aperture Uncertainty (Jitter, tj) Full 55 55 fs rms Out-of-Range Recovery Time Full 1 1 Clock Cycles 1 The maximum sample rate is the clock rate after the divider. 2 The minimum sample rate operates at 300 MSPS with L = 2 or L = 1. 3 Baud rate = 1/UI. A subset of this range can be supported. 4 Default L = 4. This number can be changed based on the sample rate and decimation ratio. 5 No DDCs used. L = 4, M = 2, F = 1. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode.
TIMING SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit
CLK+ to SYSREF+ TIMING REQUIREMENTS See Figure 2 tSU_SR Device clock to SYSREF+ setup time 117 ps tH_SR Device clock to SYSREF+ hold time −96 ps SPI TIMING REQUIREMENTS See Figure 3 tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK must be in a logic high state 10 ns tLOW Minimum period that SCLK must be in a logic low state 10 ns tACCESS Maximum time delay between falling edge of SCLK and output 6 10 ns data valid for a read operation tEN_SDIO Time required for the SDIO pin to switch from an input to an 10 ns output relative to the SCLK falling edge (not shown in Figure 3) tDIS_SDIO Time required for the SDIO pin to switch from an output to an 10 ns input relative to the SCLK rising edge (not shown in Figure 3) Rev. B | Page 9 of 72 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9234-1000 AD9234-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust CLOCK JITTER CONSIDERATIONS POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT Over JESD204B DIGITAL DOWNCONVERTER (DDC) DDC GENERAL DESCRIPTION HALF-BAND FILTER DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode at 1 GSPS Example 2: Full Bandwidth Mode at 500 MSPS Example 3: ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYSREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATION TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE