Datasheet AD8285 (Analog Devices) - 3

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Data Sheet AD8285 SPECIFICATIONS AC SPECIFICATIONS
AVDD18 = AVDD18ADC = 1.8 V, AVDD33 = AVDD33x1 = AVDD33REF = 3.3 V, DVDD18 = DVDD18CLK = 1.8 V, DVDD33SPI = DVDD33CLK = DVDD33DRV = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted.
Table 2. Parameter2 T est Conditions/Comments Min Typ Max Unit
ANALOG CHANNEL CHARACTERISTICS LNA, PGA, and AAF channels Gain 16/22/28/34 dB Gain Range 18 dB Gain Error −1.25 +1.25 dB Input Voltage Range Channel gain = 16 dB 0.25 V p-p Channel gain = 22 dB 0.125 V p-p Channel gain = 28 dB 0.0625 V p-p Channel gain = 34 dB 0.03125 V p-p Input Resistance 200 Ω input impedance selected 0.180 0.230 0.280 kΩ 200 kΩ input impedance selected 160 200 240 kΩ Input Capacitance 22 pF Input Referred Voltage Noise Maximum gain at 1 MHz 1.85 nV/√Hz Minimum gain at 1 MHz 6.03 nV/√Hz Noise Figure Maximum gain, RS = 50 Ω, unterminated 7.1 dB Maximum gain, RS = RIN = 50 Ω 12.7 dB Output Offset Gain = 16 dB −60 +60 LSB Gain = 34 dB −250 +250 LSB AAF Low-Pass Filter Cutoff −3 dB, programmable 1.0 to 12.0 MHz Tolerance After filter autotune −10 ±5 +10 % AAF Attenuation in Stop Band Third-order elliptic filter 2× cutoff 30 dB 3× cutoff 40 dB Group Delay Variation Filter set at 2 MHz 400 ns Channel-to-Channel Phase Variation Frequencies up to −3 dB −5 ±0.5 +5 Degrees ¼ of −3 dB frequency −1 +1 Degrees Channel-to-Channel Gain Matching Frequencies up to −3 dB −0.5 ±0.1 +0.5 dB ¼ of −3 dB frequency −0.25 +0.25 dB 1 dB Compression Relative to output 9.8 dBm Crosstalk −70 −55 dBc POWER SUPPLY AVDD18, AVDD18ADC 1.7 1.8 1.9 V AVDD33, AVDD33x1, AVDD33REF 3.1 3.3 3.5 V DVDD18, DVDD18CLK 1.7 1.8 1.9 V DVDD33SPI, DVDD33CLK, 3.1 3.3 3.5 V DVDD33DRV IAVDD18 Full channel mode 130 mA IAVDD33 Full channel mode 130 mA IDVDD18 22 mA IDVDD33 2 mA Total Power Dissipation Per Channel Full channel mode, no signal, typical supply 185 mW voltage × maximum supply current; excludes output current Power-Down Dissipation 5 mW Power Supply Rejection Ratio (PSRR) 1.6 mV/V Rev. B | Page 3 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Antialiasing Filter (AAF) Mux and Mux Controller ADC CLOCK INPUT CONSIDERATIONS CLOCK DUTY CYCLE CONSIDERATIONS CLOCK JITTER CONSIDERATIONS SDIO PIN SCLK PIN CS\ PIN RBIAS PIN VOLTAGE REFERENCE POWER AND GROUND RECOMMENDATIONS EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS SERIAL PERIPHERAL INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE LOGIC LEVELS RESERVED LOCATIONS DEFAULT VALUES APPLICATION DIAGRAMS OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS