Datasheet AD9675 (Analog Devices) - 9

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Data Sheet AD9675 SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, L = 2, M = 8, fSAMPLE = 40 MHz, lane data rate = 3.2 Gbps, full temperature range (0°C to 85°C), unless otherwise noted.
Table 3. Parameter1 T emperature Min Typ Max Unit
CLOCK2 Clock Rate (fSAMPLE) 40 MSPS (Mode I) Full 20.5 40 MHz 65 MSPS (Mode II) Full 20.5 65 MHz 80 MSPS (Mode III)3 Full 20.5 80 MHz 125 MSPS (Mode IV)4 Full 20.5 125 MHz Clock Pulse Width High (tEH) Full 3.75 ns Clock Pulse Width Low (tEL) Full 3.75 ns CLOCK INPUT PARAMETERS TX_TRIG± to CLK± Setup Time (tSETUP) 25°C 1 ns TX_TRIG± to CLK± Hold Time (tHOLD) 25°C 1 ns DATA OUTPUT PARAMETERS Data Output Period or Unit Interval (UI) Full L/(20 × M × fSAMPLE) Seconds Data Output Duty Cycle 25°C 50 % Data Valid Time 25°C 0.76 UI PLL Lock Time5 25°C 26 μs Wake-Up Time (Standby) 25°C 2 μs Wake-Up Time (Power-Down)6 Device 25°C 375 μs JESD204B Link 25°C 250 μs SYNCINB± Falling Edge to First K.28 Characters Full 4 Multiframes Code Group Synchronization (CGS) Phase K.28 Full 1 Multiframe Characters Duration Delay (Latency) Full ADC Pipeline Full 16 Cycles RF Decimator Full 11 Cycles Digital High-Pass Filter Full 100 Cycles TX_TRIG± to Start Code (Mode I/Mode II/Mode III/ Mode IV) Four-Lane Mode Full 31/42/30/36 Cycles Two-Lane Mode Full 31/33/30/30 Cycles Data Rate per Lane 25°C 5.0 Gbps Uncorrelated Bounded High Probability (UBHP) Jitter 25°C 11 ps Random Jitter at 2.5 Gbps Data Rate 25°C 80 ps rms Random Jitter at 5 Gbps Data Rate 25°C 46 ps rms Output Rise/Fall Time 25°C 64 ps TERMINATION CHARACTERISTICS Differential Termination Resistance Full 100 Ω APERTURE Aperture Uncertainty (Jitter) 25°C <1 ps rms Rev. A | Page 9 of 60 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications AC Specifications Digital Specifications Switching Specifications CLK±, TX_TRIG± Synchronization Timing Diagram CW Timing Diagram Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics TGC Mode CW Doppler Mode Theory of Operation TGC Operation Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Converter and Lane Configuration Configure the Tail Bits and Control Bits Set Lane Identification Values Set Number of Frames per Multiframe, K Enable Scramble, SCR Set Lane Synchronization Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing Preemphasis Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin GPOx Pins ADDRx Pins TX_TRIG± Pins Analog Test Tone Generation CW Doppler Operation Quadrature Generation I/Q Demodulator and Phase Shifter Digital RF Decimator Vector Profile RF Decimator DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter Digital Test Waveforms Waveform Generator Channel ID and Ramp Generator Digital Block Power Saving Scheme Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Recommended Start-Up Sequence Memory Map Register Table Memory Map Register Descriptions Transfer (Register 0x0FF) Profile Index and Software TX_TRIG (Register 0x10C) Outline Dimensions Ordering Guide