Datasheet AD9670 (Analog Devices)

Octal Ultrasound AFE with Digital Demodulator Data Sheet AD9670 FEATURES GENERAL DESCRIPTION 8 channels of LNA, VGA, antialiasing filter, ADC, and digital
The AD9670 is designed for low cost, low power, small size, and
demodulator/decimator
ease of use for medical ultrasound applications. It contains eight
Low power
channels of a VGA with an LNA, a CW harmonic rejection I/Q
150 mW per channel, time gain compensation (TGC) mode,
demodulator with programmable phase rotation, an antialiasing
40 MSPS
filter, an ADC, and a digital demodulator and decimator for data
62.5 mW per channel, continuous wave (CW) mode;
processing and bandwidth reduction.
<30 mW in power-down mode
Each channel features a maximum gain of up to 52 dB, a fully
10 mm × 10 mm, 144-ball CSP_BGA
differential signal path, and an active input preamplifier termination.
TGC channel, input referred noise voltage: 0.82 nV/√Hz,
The channel is optimized for high dynamic performance and
maximum gain
low power in applications where a small package size is critical.
Flexible power-down modes Fast recovery from low power standby mode: <2 μs
The LNA has a single-ended-to-differential gain that is selectable
Low noise preamplifier (LNA)
through the serial port interface (SPI). Assuming a 15 MHz noise
Input noise voltage: 0.78 nV/√Hz, gain = 21.6 dB
bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR
Programmable gain: 15.6 dB/17.9 dB/21.6 dB
is 94 dB. In CW Doppler mode, each LNA output drives an I/Q
0.1 dB input compression point: 1.00 V p-p/0.75 V p-p/
demodulator that has independently programmable phase
0.45 V p-p
rotation with 16 phase settings.
Flexible active input impedance matching
Power-down of individual channels is supported to increase
Variable gain amplifier (VGA)
battery life for portable applications. Standby mode allows quick
Attenuator range: 45 dB, linear-in-dB gain control
power-up for power cycling. In CW Doppler operation, the
Postamplifier gain (PGA): 21 dB/24 dB/27 dB/30 dB
VGA, antialiasing filter, and ADC are powered down. The ADC
Antialiasing filter
contains several features designed to maximize flexibility and
Programmable, second-order low-pass filter from 8 MHz to
minimize system cost, such as a programmable clock, data
18 MHz or 13.5 MHz to 30 MHz and high-pass filter
alignment, and programmable digital test pattern generation.
Analog-to-digital converter (ADC)
The digital test patterns include built-in fixed patterns, built-in
Signal-to-noise ratio (SNR): 75 dB, 14 bits up to 125 MSPS
pseudorandom patterns, and custom user-defined test patterns
Configurable serial low voltage differential signaling (LVDS)
entered via the SPI.
CW mode harmonic rejection I/Q demodulator Individual programmable phase rotation Dynamic range per channel: >160 dBFS/√Hz Close in SNR: 156 dBc/√Hz, 1 kHz offset, −3 dBFS Digital demodulator/decimator I/Q demodulator with programmable oscillator FIR decimation filter APPLICATIONS Medical imaging/ultrasound Nondestructive testing (NDT) Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ADC Timing Diagram CW Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CHARACTERISTICS CW DOPPLER MODE CHARACTERISTICS THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter Antialiasing Filter/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing Output Zero Stuffing SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter DIGITAL DEMODULATOR/DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband Antialiasing Filter and Decimate by 2 High-Pass Filter BASEBAND DEMODULATOR AND DECIMATOR Numerically Controlled Oscillator Decimation Filter Coefficient Memory DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator Filter Coefficients DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED STARTUP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE