Datasheet AD8284 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | Radar Receive Path AFE: 4-Channel MUX with LNA, PGA, AAF, and ADC |
| 页数 / 页 | 28 / 5 — Data Sheet. AD8284. DIGITAL SPECIFICATIONS. Table 3. Parameter. … |
| 修订版 | D |
| 文件格式/大小 | PDF / 640 Kb |
| 文件语言 | 英语 |
Data Sheet. AD8284. DIGITAL SPECIFICATIONS. Table 3. Parameter. Temperature. Min. Typ. Max. Unit
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Data Sheet AD8284 DIGITAL SPECIFICATIONS
AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.00 V internal ADC reference, fIN = 2.5 MHz, fS = 60 MSPS, RS = 50 Ω, LNA + PGA gain = 35 dB, LPF cutoff = fSAMPLECH/4, 12-bit operation, temperature = −40°C to +105°C, al specifications guaranteed by testing, unless otherwise noted.
Table 3. Parameter
1
Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)2 Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage3 Full 250 mV p-p Input Common-Mode Voltage Full 1.2 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF LOGIC INPUTS (PDWN, SCLK, AUX, MUX[0], MUX[1], ZSEL)2 Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (CS)2 Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 70 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (SDI)2 Logic 1 Voltage Full 1.2 DVDD33x + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF LOGIC OUTPUT (SDO) Logic 1 Voltage (IOH = 800 μA) Full 3.0 V Logic 0 Voltage (IOL = 50 μA) Full 0.3 V LOGIC OUTPUTS (D11 to D0, SFLAG) Logic 1 Voltage (IOH = 2 mA) Full 3.0 V Logic 0 Voltage (IOL = 2 mA) Full 0.3 V 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and testing methodology. 2 Guaranteed by design only. 3 Specified for LVDS and LVPECL only. Rev. D | Page 5 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing and Switching Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Multiplexer Low Noise Amplifier Recommendation Antialiasing Filter Saturation Flag ADC AUX Channel Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDI and SDO Pins SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Caution Logic Levels Reserved Locations Default Values Application Circuits Packaging and Ordering Information Outline Dimensions Ordering Guide Automotive Products
AVDD18x = 1.8 V, AVDD33x = 3.3 V, DVDD18x = 1.8 V, DVDD33x = 3.3 V, 1.00 V internal ADC reference, fIN = 2.5 MHz, fS = 60 MSPS, RS = 50 Ω, LNA + PGA gain = 35 dB, LPF cutoff = fSAMPLECH/4, 12-bit operation, temperature = −40°C to +105°C, al specifications guaranteed by testing, unless otherwise noted.
Table 3. Parameter
1
Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)2 Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage3 Full 250 mV p-p Input Common-Mode Voltage Full 1.2 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF LOGIC INPUTS (PDWN, SCLK, AUX, MUX[0], MUX[1], ZSEL)2 Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (CS)2 Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 70 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (SDI)2 Logic 1 Voltage Full 1.2 DVDD33x + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF LOGIC OUTPUT (SDO) Logic 1 Voltage (IOH = 800 μA) Full 3.0 V Logic 0 Voltage (IOL = 50 μA) Full 0.3 V LOGIC OUTPUTS (D11 to D0, SFLAG) Logic 1 Voltage (IOH = 2 mA) Full 3.0 V Logic 0 Voltage (IOL = 2 mA) Full 0.3 V 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and testing methodology. 2 Guaranteed by design only. 3 Specified for LVDS and LVPECL only. Rev. D | Page 5 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing and Switching Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Multiplexer Low Noise Amplifier Recommendation Antialiasing Filter Saturation Flag ADC AUX Channel Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDI and SDO Pins SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Caution Logic Levels Reserved Locations Default Values Application Circuits Packaging and Ordering Information Outline Dimensions Ordering Guide Automotive Products