Datasheet LTM9011-14, LTM9010-14, LTM9009-14 (Analog Devices) - 6

LTM9011-14/ LTM9010-14/LTM9009-14 POWER REQUIREMENTS
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTM9011-14 LTM9010-14 LTM9009-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Wave Input l 582 632 476 508 395 450 mA IOVDD Digital Supply Current 2-Lane Mode, 1.75mA Mode l 54 62 52 62 50 58 mA 2-Lane Mode, 3.5mA Mode l 98 108 96 106 94 104 mA PDISS Power Dissipation 2-Lane Mode, 1.75mA Mode l 1145 1249 950 1026 801 914 mW 2-Lane Mode, 3.5mA Mode l 1224 1332 1030 1105 880 997 mW PSLEEP Sleep Mode Power 2 2 2 mW PNAP Nap Mode Power 170 170 170 mW PDIFFCLK Power Decrease With Single-Ended Encode Mode Enabled 40 40 40 mW (No Decrease for Sleep Mode) TIMING CHARACTERISTICS
The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTM9011-14 LTM9010-14 LTM9009-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Notes 10,11) l 5 125 5 105 5 80 MHz tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 100 4.52 4.76 100 5.93 6.25 100 ns Duty Cycle Stabilizer On l 2 4 100 2 4.76 100 2 6.25 100 ns tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 3.8 4 100 4.52 4.76 100 5.93 6.25 100 ns Duty Cycle Stabilizer On l 2 4 100 2 4.76 100 2 6.25 100 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)
tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization 1/(8 • fS) s 2-Lanes, 14-Bit Serialization 1/(7 • fS) s 2-Lanes, 12-Bit Serialization 1/(6 • fS) s 1-Lane, 16-Bit Serialization 1/(16 • fS) s 1-Lane, 14-Bit Serialization 1/(14 • fS) s 1-Lane, 12-Bit Serialization 1/(12 • fS) s tFRAME FR to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tDATA DATA to DCO Delay (Note 8) l 0.35 • tSER 0.5 • tSER 0.65 • tSER s tPD Propagation Delay (Note 8) l 0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s tR Output Rise Time Data, DCO, FR, 20% to 80% 0.17 ns tF Output Fall Time Data, DCO, FR, 20% to 80% 0.17 ns DCO Cycle-Cycle Jitter tSER = 1ns 60 psP-P Pipeline Latency 6 Cycles Rev D 6 For more information www.analog.com Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Pin Configuration Table Functional Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts