Datasheet AD8283 (Analog Devices) - 5
| 制造商 | Analog Devices |
| 描述 | Radar Receive Path AFE: 6-Channel LNA/PGA/AAF with ADC |
| 页数 / 页 | 27 / 5 — Data Sheet. AD8283. DIGITAL SPECIFICATIONS. Table 3. Parameter. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 604 Kb |
| 文件语言 | 英语 |
Data Sheet. AD8283. DIGITAL SPECIFICATIONS. Table 3. Parameter. Temperature. Min. Typ. Max. Unit
该数据表的模型线
文件文字版本
Data Sheet AD8283 DIGITAL SPECIFICATIONS
AVDD18x = 1.8 V, AVDD33 = 3.3 V, DVDD18 = 1.8 V, DVDD33 = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted.
Table 3. Parameter
1
Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 mV p-p Input Common-Mode Voltage Full 1.2 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF LOGIC INPUTS (PDWN, SCLK, AUX, MUXA, ZSEL) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (CS) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 70 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (SDIO) Logic 1 Voltage Full 1.2 DVDD33x + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF LOGIC OUTPUT (SDIO)3 Logic 1 Voltage (IOH = 800 μA) Full 3.0 V Logic 0 Voltage (IOL = 50 μA) Full 0.3 V LOGIC OUTPUT (D[11:0], DSYNC) Logic 1 Voltage (IOH = 2 mA) Full 3.0 V Logic 0 Voltage (IOL = 2 mA) Full 0.05 V 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Specified for LVDS and LVPECL only. 3 Specified for 13 SDIO pins sharing the same connection. Rev. C | Page 5 of 27 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Low Noise Amplifier (LNA) Recommendation Antialiasing Filter (AAF) Mux and Mux Controller ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDIO Pin SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Serial Peripheral Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Logic Levels Reserved Locations Default Values Application Diagrams Outline Dimensions Ordering Guide Automotive Products
AVDD18x = 1.8 V, AVDD33 = 3.3 V, DVDD18 = 1.8 V, DVDD33 = 3.3 V, 1.024 V internal ADC reference, fIN = 2.5 MHz, fSAMPLE = 72 MSPS, RS = 50 Ω, LNA + PGA gain = 34 dB, LPF cutoff = fSAMPLECH/4, full channel mode, 12-bit operation, temperature = −40°C to +105°C, unless otherwise noted.
Table 3. Parameter
1
Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−) Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 mV p-p Input Common-Mode Voltage Full 1.2 V Input Resistance (Differential) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF LOGIC INPUTS (PDWN, SCLK, AUX, MUXA, ZSEL) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (CS) Logic 1 Voltage Full 1.2 3.6 V Logic 0 Voltage Full 0.3 V Input Resistance 25°C 70 kΩ Input Capacitance 25°C 0.5 pF LOGIC INPUT (SDIO) Logic 1 Voltage Full 1.2 DVDD33x + 0.3 V Logic 0 Voltage Full 0 0.3 V Input Resistance 25°C 30 kΩ Input Capacitance 25°C 2 pF LOGIC OUTPUT (SDIO)3 Logic 1 Voltage (IOH = 800 μA) Full 3.0 V Logic 0 Voltage (IOL = 50 μA) Full 0.3 V LOGIC OUTPUT (D[11:0], DSYNC) Logic 1 Voltage (IOH = 2 mA) Full 3.0 V Logic 0 Voltage (IOL = 2 mA) Full 0.05 V 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. 2 Specified for LVDS and LVPECL only. 3 Specified for 13 SDIO pins sharing the same connection. Rev. C | Page 5 of 27 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Low Noise Amplifier (LNA) Recommendation Antialiasing Filter (AAF) Mux and Mux Controller ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDIO Pin SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Serial Peripheral Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Logic Levels Reserved Locations Default Values Application Diagrams Outline Dimensions Ordering Guide Automotive Products