Datasheet AD6641 (Analog Devices) - 3

AD6641
The data stored in the FIFO can be read back based on several
PRODUCT HIGHLIGHTS
user-selectable output modes. The DUMP pin can be asserted 1. High Performance ADC Core. to output the FIFO data. The data stored in the FIFO can be Maintains 65.8 dBFS SNR at 500 MSPS with a 250 MHz input. accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit 2. Low Power. DDR LVDS interface. The maximum output throughput Consumes only 695 mW at 500 MSPS. supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR 3. Ease of Use. LVDS mode and is internally limited to 1/8th of the maximum On-chip 16k FIFO allows the user to target the high perfor- input sample rate. This corresponds to the maximum output mance ADC to the time period of interest and reduce the data rate of 62.5 MHz at an input clock rate of 500 MSPS. constraints of processing the data by transferring it at an The ADC requires a 1.9 V analog voltage supply and a differen- arbitrary time and a lower sample rate. The on-chip refer- tial clock for full performance operation. Output format options ence and sample-and-hold provide flexibility in system include twos complement, offset binary format, or Gray code. A design. Use of a single 1.9 V supply simplifies system power data clock output is available for proper output data timing. Fabri- supply design. cated on an advanced SiGe BiCMOS process, the device is 4. Serial Port Control. available in a 56-lead LFCSP and is specified over the industrial Standard serial port interface supports configuration of the temperature range (−40°C to +85°C). This product is protected device and customization for the user’s needs. by a U.S. patent. 5. 1.9 V or 3.3 V SPI and Serial Data Port Operation. Rev. 0 | Page 3 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS SPI TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS SPI REGISTER MAP THEORY OF OPERATION FIFO OPERATION Single Capture Mode Fill Pin Timing Dump Pin Timing SPORT Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High SCLK Signal (5) SDFS Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Parallel Master Mode (Single Capture) Fill Pulse (1) Empty Signal (2) Full Signal (3) Dump Signal (4)—Transition to High PCLK± Signal (5) PD[11:0] Signal (6) Dump Signal (7)—Transition to Low Empty Signal (8)—Transition to High Continuous Capture Mode FIFO OUTPUT INTERFACES SPORT Interface Serial Data Frame (Serial Bus Master) CMOS Output Interface LVDS Output Interface ANALOG INPUT AND VOLTAGE REFERENCE VREF CONFIGURATION USING THE SPI OUTLINE DIMENSIONS ORDERING GUIDE