Datasheet AD9286 (Analog Devices) - 6

AD9286 Data Sheet SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.
Table 4. Parameter Temperature Min Typ Max Unit
CLOCK INPUT PARAMETERS Input Clock Rate Full 60 500 MHz CLK Period (tCLK) Full 2 Ns CLK Pulse Width High (tCH) Full 1 Ns DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) 3.7 ns DCO Propagation Delay (tDCO) Full 3.7 ns DCO to Data Skew (tSKEW) Full −280 −60 100 ps Pipeline Delay (Latency) Full 11 Cycles Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms Wake-Up Time1 Full 500 μs OUT-OF-RANGE RECOVERY TIME Full 4 Cycles 1 Wake-up time is dependent on the value of the decoupling capacitors.
SPI TIMING SPECIFICATIONS Table 5. Parameter Description Min Typ Max Unit
SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH SCLK pulse width high 10 ns tLOW SCLK pulse width low 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input 10 ns to an output relative to the SCLK falling edge tDIS_SDIO Time required for the SDIO pin to switch from an output 10 ns to an input relative to the SCLK rising edge
Timing Diagrams M – 1 M + 4 M + 5 M VIN1+, VIN1– M + 3 tA M + 1 M + 2 N – 1 N – 2 N + 4 N + 3 VIN2+, VIN2– N N + 2 N + 1 tA t t CLK CH CLK+ CLK– tDCO DCO+, DCO– tSKEW DATA M – 11 N – 11 M – 10 N – 10 M – 9 N – 9 M – 8 N – 8 M – 7
002
t
338-
PD
09 Figure 2. Output Timing Diagram, Sample Mode = Interleaved (Default) Rev. C | Page 6 of 27 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS SPI TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations VOLTAGE REFERENCE RBIAS CLOCK INPUT CONSIDERATIONS Clock Input Options Clocking Modes Interleave Performance DIGITAL OUTPUTS Digital Output Enable Function () BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Voltage Reference (Register 0x18) Bits[7:5]—Reserved Bits[4:0]—Voltage Reference APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE