Datasheet AD9467-EP (Analog Devices)

16-Bit, 250 MSPS Analog-to-Digital Converter Enhanced Product AD9467-EP FEATURES FUNCTIONAL BLOCK DIAGRAM 75.5 dBFS SNR to 210 MHz at 250 MSPS AVDD1 AVDD2 AVDD3 SPIVDD DRVDD (1.8V) (3.3V) (1.8V) (1.8V TO 3.3V) (1.8V) 90 dBFS SFDR to 300 MHz at 250 MSPS CSB 60 fs rms jitter AD9467-EP SDIO Excellent linearity at 250 MSPS BUFFER SCLK VIN+ 16 DNL = ±0.5 LSB typical PIPELINE 2 VIN– ADC LVDS OR+/OR– INL = ±3.5 LSB typical OUTPUT 16 D15+/D15– STAGING TO 2 V p-p to 2.5 V p-p (default) differential full-scale D0+/D0– input (programmable) CLK+ CLOCK 2 AND TIMING DCO+/DCO– Integrated input buffer CLK– MANAGEMENT REF External reference support option
001
Clock duty cycle stabilizer AGND XVREF DRGND
14751-
Output clock available
Figure 1.
Serial port control Built-in selectable digital test pattern generation Selectable output data format LVDS outputs (ANSI-644 compatible) 1.8 V and 3.3 V supply operation ENHANCED PRODUCT FEATURES
A data clock output (DCO) for capturing data on the output is
Extended temperature range (−55°C to +125°C)
provided for signaling a new output bit. The internal power-
Controlled manufacturing baseline
down feature, when enabled via the serial port interface (SPI),
Qualification data available on request
typically consumes less than 5 mW.
APPLICATIONS
Optional features allow users to implement various selectable operating conditions, including input range, data format select,
Multicarrier, multimode cellular receivers
and output data test patterns.
Antenna array positioning Power amplifier linearization
The AD9467-EP is available in a Pb-free, 72-lead, LFCSP specified
Broadband wireless
over the −55°C to +125°C extended temperature range.
Radar
Additional application and technical information can be found
Infrared imaging
in the AD9467 data sheet.
Communications instrumentation PRODUCT HIGHLIGHTS GENERAL DESCRIPTION
1. IF optimization capability used to improve SFDR. The AD9467-EP is a 16-bit, monolithic, IF sampling analog-to- 2. Outstanding SFDR performance for IF sampling digital converter (ADC). It is optimized for high performance applications such as multicarrier, multimode 3G, and 4G over wide bandwidths and ease of use. The product operates at a cellular base station receivers. 250 MSPS conversion rate and is designed for wireless receivers, 3. Ease of use: on-chip reference, high input impedance instrumentation, and test equipment that require a high buffer, adjustable analog input range, and an output clock dynamic range. to simplify data capture. The ADC requires 1.8 V and 3.3 V power supplies and a low 4. Packaged in a Pb-free, 72-lead LFCSP package. voltage differential input clock for full performance operation. 5. Clock duty cycle stabilizer (DCS) maintains overall ADC No external reference or driver components are required for performance over a wide range of input clock pulse widths. many applications. Data outputs are LVDS-compatible (ANSI-644- 6. Standard SPI supports various product features and functions, compatible) and include the means to reduce the overal current such as data formatting (offset binary, twos complement, or needed for short trace distances. Gray coding).
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Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE