Datasheet AD9266-EP (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 20/40/65/80 MSPS, 1.8 V Analog-to-Digital Converter |
| 页数 / 页 | 12 / 7 — Enhanced Product. AD9266-EP. SWITCHING SPECIFICATIONS. Table 4. … |
| 修订版 | B |
| 文件格式/大小 | PDF / 241 Kb |
| 文件语言 | 英语 |
Enhanced Product. AD9266-EP. SWITCHING SPECIFICATIONS. Table 4. Parameter. Temp Min Typ Max Unit. N + 6. N – 1. N + 7. N + 1. N + 5. VIN
该数据表的模型线
文件文字版本
Enhanced Product AD9266-EP SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted.
Table 4. Parameter Temp Min Typ Max Unit
CLOCK INPUT PARAMETERS Input Clock Rate Full 520 MHz Conversion Rate1 Full 3 65 MSPS CLK Period—Divide by 1 Mode (tCLK) Full 15.38 ns CLK Pulse Width High (tCH) 7.69 ns Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 3 ns DCO Propagation Delay (tDCO) Full 3 ns DCO to Data Skew (tSKEW) Full 0.1 ns Pipeline Delay (Latency) Full 8 Cycles Wake-Up Time2 Full 350 μs Standby Full 300 ns OUT-OF-RANGE RECOVERY TIME Full 2 Cycles 1 Conversion rate is the clock rate after the CLK divider. 2 Wake-up time is dependent on the value of the decoupling capacitors.
tA N N + 6 N – 1 N + 7 N + 1 N + 5 VIN N + 8 N + 2 N + 3 tCLK CLK+ CLK– tDCO DCO t t SKEW SKEW D1_D0 D1N–9 D0N–9 D1N–8 D0N–8 D1N–7 D0N–7 D1N–6 D0N–6 D1N–5 D0N–5 D1N–4 D0N–4 tPD
02 0
D15N–9 D14
6-
D15_D14 N–9 D15N–8 D14N–8 D15N–7 D14N–7 D15N–6 D14N–6 D15N–5 D14N–5 D15N–4 D14N–4
047 1 Figure 2. CMOS Output Data Timing Rev. B | Page 7 of 12 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle clock, DCS disabled, unless otherwise noted.
Table 4. Parameter Temp Min Typ Max Unit
CLOCK INPUT PARAMETERS Input Clock Rate Full 520 MHz Conversion Rate1 Full 3 65 MSPS CLK Period—Divide by 1 Mode (tCLK) Full 15.38 ns CLK Pulse Width High (tCH) 7.69 ns Aperture Delay (tA) Full 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 ps rms DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Full 3 ns DCO Propagation Delay (tDCO) Full 3 ns DCO to Data Skew (tSKEW) Full 0.1 ns Pipeline Delay (Latency) Full 8 Cycles Wake-Up Time2 Full 350 μs Standby Full 300 ns OUT-OF-RANGE RECOVERY TIME Full 2 Cycles 1 Conversion rate is the clock rate after the CLK divider. 2 Wake-up time is dependent on the value of the decoupling capacitors.
tA N N + 6 N – 1 N + 7 N + 1 N + 5 VIN N + 8 N + 2 N + 3 tCLK CLK+ CLK– tDCO DCO t t SKEW SKEW D1_D0 D1N–9 D0N–9 D1N–8 D0N–8 D1N–7 D0N–7 D1N–6 D0N–6 D1N–5 D0N–5 D1N–4 D0N–4 tPD
02 0
D15N–9 D14
6-
D15_D14 N–9 D15N–8 D14N–8 D15N–7 D14N–7 D15N–6 D14N–6 D15N–5 D14N–5 D15N–4 D14N–4
047 1 Figure 2. CMOS Output Data Timing Rev. B | Page 7 of 12 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE