Datasheet AD9277 (Analog Devices)

Octal LNA/VGA/AAF/14-Bit ADC and CW I/Q Demodulator AD9277 FEATURES APPLICATIONS 8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator Medical imaging/ultrasound Low noise preamplifier (LNA) Automotive radar Input-referred noise: 0.75 nV/√Hz typical at 5 MHz (gain = 21.3 dB) PRODUCT HIGHLIGHTS SPI-programmable gain: 15.6 dB/17.9 dB/21.3 dB
1. Small Footprint.
Single-ended input: VIN maximum = 733 mV p-p/
Eight channels are contained in a small, space-saving
550 mV p-p/367 mV p-p Dual-mode active input impedance matching
package. Full TGC path, ADC, and I/Q demodulator
Bandwidth (BW) > 100 MHz
contained within a 100-lead, 16 mm × 16 mm TQFP.
Full-scale (FS) output: 4.4 V p-p differential
2. Low Power.
Variable gain amplifier (VGA)
In TGC mode, low power of 207 mW per channel
Attenuator range: −42 dB to 0 dB
at 50 MSPS. In CW mode, ultralow power of 94 mW
Postamp gain: 21 dB/24 dB/27 dB/30 dB
per channel.
Linear-in-dB gain control Antialiasing filter (AAF)
3. Integrated High Dynamic Range I/Q Demodulator with
Programmable second-order LPF from 8 MHz to 18 MHz
Phase Rotation.
Programmable HPF
4. Ease of Use.
Analog-to-digital converter (ADC)
A data clock output (DCO±) operates up to 480 MHz
14 bits at 10 MSPS to 50 MSPS
and supports double data rate (DDR) operation.
SNR: 73 dB
5. User Flexibility.
SFDR: 75 dB Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Serial port interface (SPI) control offers a wide range of
Data and frame clock outputs
flexible features to meet specific system requirements.
CW mode I/Q demodulator
6. Integrated Second-Order Antialiasing Filter.
Individual programmable phase rotation
This filter is placed before the ADC and is programmable
Output dynamic range per channel >160 dBFS/√Hz
from 8 MHz to 18 MHz.
Low power: 207 mW per channel at 14 bits/50 MSPS (TGC), 94 mW per channel for CW Doppler Flexible power-down modes Overload recovery in <10 ns Fast recovery from low power standby mode: <2 μs 100-lead TQFP_EP FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 PDWN STBY DRVDD LO-A TO LO-H I/Q DEMODULATOR 8 CHANNELS LOSW-A TO LOSW-H LI-A TO LI-H 14-BIT SERIAL DOUTA+ TO DOUTH+ LNA VGA LG-A TO LG-H AAF ADC LVDS DOUTA– TO DOUTH– FCO+ SERIAL DATA LO FCO– REFERENCE PORT RATE GENERATION DCO+ INTERFACE MULTIPLIER DCO– + – + – – + I– F I+ B K + O O
1
IN IN Q Q E IO AS L K K– SET 0:3] CS
00
E 4L 4L CW CW VR SD
1-
GA GA CW CW O[ SC CL CL R RBI
18
GP
08 Figure 1.
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Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information TGC OPERATION Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode DIGITAL OUTPUTS AND TIMING SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS APPLICATIONS INFORMATION POWER AND GROUND RECOMMENDATIONS EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE