Datasheet AD9277 (Analog Devices) - 10
| 制造商 | Analog Devices |
| 描述 | Octal LNA/VGA/AAF/14-Bit ADC and CW I/Q Demodulator |
| 页数 / 页 | 48 / 10 — AD9277. ABSOLUTE MAXIMUM RATINGS. Table 4. Parameter Rating. THERMAL … |
| 文件格式/大小 | PDF / 1.0 Mb |
| 文件语言 | 英语 |
AD9277. ABSOLUTE MAXIMUM RATINGS. Table 4. Parameter Rating. THERMAL IMPEDANCE. Table 5. Airflow Velocity (m/s). θ 1. θJB. θJC Unit
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AD9277 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating
Stresses above those listed under Absolute Maximum Ratings AVDD1 to GND −0.3 V to +2.0 V may cause permanent damage to the device. This is a stress AVDD2 to GND −0.3 V to +3.9 V rating only; functional operation of the device at these or any DRVDD to GND −0.3 V to +2.0 V other conditions above those indicated in the operational GND to GND −0.3 V to +0.3 V section of this specification is not implied. Exposure to absolute AVDD2 to AVDD1 −2.0 V to +3.9 V maximum rating conditions for extended periods may affect AVDD1 to DRVDD −2.0 V to +2.0 V device reliability. AVDD2 to DRVDD −2.0 V to +3.9 V
THERMAL IMPEDANCE
Digital Outputs (DOUTx+, DOUTx−, −0.3 V to +2.0 V DCO+, DCO−, FCO+, FCO−) to GND
Table 5.
CLK+, CLK−, SDIO to GND −0.3 V to +2.0 V
Airflow Velocity (m/s) θ 1 JA θJB θJC Unit
LI-x, LO-x, LOSW-x to GND −0.3 V to +3.9 V 0.0 20.3 °C/W CWI−, CWI+, CWQ−, CWQ+ to GND −0.3 V to +3.9 V 1.0 14.4 7.6 4.7 °C/W PDWN, STBY, SCLK, CSB to GND −0.3 V to +2.0 V 2.5 12.9 °C/W GAIN+, GAIN−, RESET, 4LO+, 4LO−, −0.3 V to +3.9 V 1 GPO0, GPO1, GPO2, GPO3 to GND θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB. RBIAS, VREF to GND −0.3 V to +2.0 V Operating Temperature Range (Ambient) −40°C to +85°C
ESD CAUTION
Storage Temperature Range (Ambient) −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Rev. 0 | Page 10 of 48 Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information TGC OPERATION Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode DIGITAL OUTPUTS AND TIMING SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS APPLICATIONS INFORMATION POWER AND GROUND RECOMMENDATIONS EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE
AD9277 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating
Stresses above those listed under Absolute Maximum Ratings AVDD1 to GND −0.3 V to +2.0 V may cause permanent damage to the device. This is a stress AVDD2 to GND −0.3 V to +3.9 V rating only; functional operation of the device at these or any DRVDD to GND −0.3 V to +2.0 V other conditions above those indicated in the operational GND to GND −0.3 V to +0.3 V section of this specification is not implied. Exposure to absolute AVDD2 to AVDD1 −2.0 V to +3.9 V maximum rating conditions for extended periods may affect AVDD1 to DRVDD −2.0 V to +2.0 V device reliability. AVDD2 to DRVDD −2.0 V to +3.9 V
THERMAL IMPEDANCE
Digital Outputs (DOUTx+, DOUTx−, −0.3 V to +2.0 V DCO+, DCO−, FCO+, FCO−) to GND
Table 5.
CLK+, CLK−, SDIO to GND −0.3 V to +2.0 V
Airflow Velocity (m/s) θ 1 JA θJB θJC Unit
LI-x, LO-x, LOSW-x to GND −0.3 V to +3.9 V 0.0 20.3 °C/W CWI−, CWI+, CWQ−, CWQ+ to GND −0.3 V to +3.9 V 1.0 14.4 7.6 4.7 °C/W PDWN, STBY, SCLK, CSB to GND −0.3 V to +2.0 V 2.5 12.9 °C/W GAIN+, GAIN−, RESET, 4LO+, 4LO−, −0.3 V to +3.9 V 1 GPO0, GPO1, GPO2, GPO3 to GND θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB. RBIAS, VREF to GND −0.3 V to +2.0 V Operating Temperature Range (Ambient) −40°C to +85°C
ESD CAUTION
Storage Temperature Range (Ambient) −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Rev. 0 | Page 10 of 48 Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information TGC OPERATION Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode DIGITAL OUTPUTS AND TIMING SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS APPLICATIONS INFORMATION POWER AND GROUND RECOMMENDATIONS EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE