Datasheet ADW12001 (Analog Devices)

14-Bit, 40 MSPS Dual Analog-to-Digital Converter ADW12001 FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD AGND Integrated dual 14-bit ADC Single 3 V supply operation: 2.7 V to 3.6 V OTR_A VIN+_A Differential input with 500 MHz, 3 dB bandwidth 14 14 D13_A TO D0_A SHA ADC OUTPUT Flexible analog input: 1 V p-p to 2 V p-p range VIN–_A MUX/ OEB_A BUFFERS Offset binary or twos complement data format Clock duty cycle stabilizer REFT_A MUX_SELECT Output datamux option REFB_A CLK_A CLOCK DUTY CYCLE CLK_B APPLICATIONS VREF STABILIZER DCS SENSE Ultrasound equipment SHARED_REF AGND 0.5V Direct conversion or IF sampling receivers PWDN_A MODE WB-CDMA, CDMA2000, WiMAX PWDN_B CONTROL DFS Battery-powered instruments REFT_B Hand-held scopemeters REFB_B Low cost digital oscilloscopes VIN+_B OTR_B SHA ADC 14 OUTPUT 14 VIN–_B D13_B TO D0_B MUX/ GENERAL DESCRIPTION BUFFERS OEB_B
The ADW12001 is a dual, 3 V, 14-bit, 40 MSPS analog-to-
ADW12001
1 digital converter (ADC). It features dual high performance 00 7-
DRVDD DRGND
773 sample-and-hold amplifiers (SHAs) and an integrated voltage 0 Figure 1. reference. The ADW12001 uses a multistage differential pipelined architecture with output error correction logic to Fabricated on an advanced CMOS process, the ADW12001 provide 14-bit accuracy and to guarantee no missing codes is available in a Pb-free, space saving, 64-lead LFCSP and over the full operating temperature. The wide bandwidth is specified over the industrial temperature range (−40°C differential SHA allows for a variety of user-selectable input to +115°C). ranges and offsets, including single-ended applications. It is
PRODUCT HIGHLIGHTS
suitable for various applications, including multiplexed systems 1. Pin compatible with the AD9238, 12-bit 40 MSPS ADC. that switch full-scale voltage levels in successive channels and 2. Low power consumption: 40 MSPS = 330 mW. for sampling inputs at frequencies well beyond the Nyquist rate. 3. Typical channel isolation of 85 dB @ fIN = 10 MHz. Dual single-ended clock inputs are used to control all internal 4. The clock duty cycle stabilizer maintains performance over conversion cycles. A duty cycle stabilizer is available and can a wide range of clock duty cycles. compensate for wide variations in the clock duty cycle, allowing 5. Multiplexed data output option enables single port the converter to maintain excellent performance. The digital operation from either Data Port A or Data Port B. output data is presented in either straight binary or twos com- plement format. Out-of-range signals indicate an overflow condition, which can be used with the most significant bit to determine low or high overflow.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING DATA FORMAT VOLTAGE REFERENCE Internal Reference Connection External Reference Operation THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE