Datasheet AD9218-EP (Analog Devices) - 9

Enhanced Product AD9218-EP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ) A (MSB A A A A A A A A D NC DD ND V E V G D9 D8 D7 D6 D5 D4 D3 D2 48 47 46 45 44 43 42 41 40 39 38 37 GND 1 36 D1A AINA 2 35 D0A AINA 3 34 GND DFS/GAIN 4 33 VDD REFINA 5 32 GND AD9218-EP REFOUT 6 31 VD TOP VIEW REFINB 7 30 V (Not to Scale) D S1 8 29 GND S2 9 28 VDD AINB 10 27 GND AINB 11 26 D0B GND 12 25 D1B 13 14 15 16 17 18 19 20 21 22 23 24 D B B B B B B B B B V DD ND 9 NC V G D8 D7 D6 D5 D4 D3 D2 E ) D
005
(MSB
17309- Figure 5. Pin Configuration
Table 7. Pin Function Descriptions Pin Number Mnemonic Description
1, 12, 16, 27, 29, GND Ground. 32, 34, 45 2 AINA Analog Input for Channel A. 3 A A Analog Input for Channel A (Complementary). IN 4 DFS/GAIN Data Format Select and Analog Input Gain Mode. Low = offset binary output available, 1 V p-p supported; high = twos complement output available, 1 V p-p supported. 5 REFINA Reference Voltage Input for Channel A. 6 REFOUT Internal Reference Voltage. 7 REFINB Reference Voltage Input for Channel B. 8 S1 User Select 1. 9 S2 User Select 2. 10 A B Analog Input for Channel B (Complementary). IN 11 AINB Analog Input for Channel B. 13, 30, 31, 48 VD Analog Supply. 14 ENCB Encode B. Clock input for Channel B. 15, 28, 33, 46 VDD Digital Supply. 17 to 26 D9B to D0B Digital Output for Channel B (D9B = MSB). 35 to 44 D0A to D9A Digital Output for Channel A (D9A = MSB). 47 ENCA Encode A. Clock input for Channel A. Rev. 0 | Page 9 of 11 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE