Datasheet AD9203W (Analog Devices) - 4
| 制造商 | Analog Devices |
| 描述 | 10-Bit, 40 MSPS, Low-Power Analog-to-Digital Converter |
| 页数 / 页 | 8 / 4 — AD9203W. Automotive Product. Parameter. Symbol Min. Typ. Max. Unit. … |
| 文件格式/大小 | PDF / 132 Kb |
| 文件语言 | 英语 |
AD9203W. Automotive Product. Parameter. Symbol Min. Typ. Max. Unit. Conditions. N+1. N+2. N–1. N+3. ANALOG. INPUT. N+6. N+4. N+5. CLOCK. DATA. N–7. N–6. N–5. N–4
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AD9203W Automotive Product Parameter Symbol Min Typ Max Unit Conditions
Two-Tone Intermodulation Distortion IMD 68 dB f = 44.49 MHz and 45.52 MHz Differential Phase DP 0.2 Degree NTSC 40 IRE ramp Differential Gain DG 0.3 % DIGITAL INPUTS High Input Voltage VIH 2.0 V Low Input Voltage VIL 0.4 V Clock Pulse Width High 11.25 ns Clock Pulse Width Low 11.25 ns Clock Period2 25 ns DIGITAL OUTPUTS High-Z Leakage IOZ ± 5.0 μA Output = 0 to DRVDD Data Valid Delay tOD 5 ns CL = 20 pF Data Enable Delay tDEN 6 ns CL = 20 pF Data High-Z Delay tDHZ 6 ns CL = 20 pF LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 μA) VOH 2.95 V High Level Output Voltage (IOH = 0.5 mA) VOH 2.80 V Low Level Output Voltage (IOL= 1.6 mA) VOL 0.3 V Low Level Output Voltage (IOL= 50 μA) VOL 0.05 V 1 Differential Input (2 V p-p). 2 The AD9203W converts at clock rates as low as 20 kHz.
N+1 N N+2 N–1 N+3 ANALOG INPUT N+6 N+4 N+5 CLOCK DATA N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 OUT TOD = 3ns MIN
02
7ns MAX
0 58-
(CLOAD = 20pF)
102 Figure 2. Timing Diagram Rev. 0 | Page 4 of 8 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
AD9203W Automotive Product Parameter Symbol Min Typ Max Unit Conditions
Two-Tone Intermodulation Distortion IMD 68 dB f = 44.49 MHz and 45.52 MHz Differential Phase DP 0.2 Degree NTSC 40 IRE ramp Differential Gain DG 0.3 % DIGITAL INPUTS High Input Voltage VIH 2.0 V Low Input Voltage VIL 0.4 V Clock Pulse Width High 11.25 ns Clock Pulse Width Low 11.25 ns Clock Period2 25 ns DIGITAL OUTPUTS High-Z Leakage IOZ ± 5.0 μA Output = 0 to DRVDD Data Valid Delay tOD 5 ns CL = 20 pF Data Enable Delay tDEN 6 ns CL = 20 pF Data High-Z Delay tDHZ 6 ns CL = 20 pF LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 μA) VOH 2.95 V High Level Output Voltage (IOH = 0.5 mA) VOH 2.80 V Low Level Output Voltage (IOL= 1.6 mA) VOL 0.3 V Low Level Output Voltage (IOL= 50 μA) VOL 0.05 V 1 Differential Input (2 V p-p). 2 The AD9203W converts at clock rates as low as 20 kHz.
N+1 N N+2 N–1 N+3 ANALOG INPUT N+6 N+4 N+5 CLOCK DATA N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 OUT TOD = 3ns MIN
02
7ns MAX
0 58-
(CLOAD = 20pF)
102 Figure 2. Timing Diagram Rev. 0 | Page 4 of 8 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE