Datasheet AD8335 (Analog Devices) - 4

AD8335 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
Two-Tone IMD3 Distortion VOUT = 1 V p-p, VGN = 3 V f1 = 1 MHz, f2 = 1.05 MHz −69 dBc f1 = 10 MHz, f2 = 10.05 MHz −65 dBc Output IP3 (OIP3) VOUT = 1 V p-p, VGN = 3 V f = 1 MHz 33 dBm f = 10 MHz 31 dBm Channel-to-Channel Crosstalk VOUT = 1 V p-p, f = 1 to 10 MHz −80 dBc Overload Recovery PrA or VGA 10 ns Group Delay Variation Full gain range, f = 1 MHz to 10 MHz 3.0 ns GAIN CONTROL INTERFACE VGNx pins Normal Operating Range 0 3 V Maximum Range No gain foldover 0 VS V Gain Range Low gain mode; (HLxx pins = 0 V) −10 to +38 dB High gain mode; (HLxx pins = VS) −2 to +46 dB Scale Factor Nominal (Pin SL12 and Pin SL34 = 2.5 V) 19.1 20.1 21.1 dB/V Bias Current −0.3 μA Response Bandwidth 5 MHz Response Time 48 dB gain change 350 ns GAIN ACCURACY VGNx pins Absolute Gain Error 0 ≤ VGN ≤ 0.4 V 1.25 7.5 dB 0.4 ≤ VGN ≤ 2.6 V, 1σ −1.25 ±0.2 +1.25 dB 2.6 ≤ VGN ≤ 3 V −7.5 −1.25 dB Gain Law Conformance Over Temperature 0.4 ≤ VGN ≤ 2.6 V; −40°C < TA< +85°C ±0.75 dB Intercept Low gain mode; PrA matched to 50 Ω −16.1 dB High gain mode; PrA matched to 50 Ω −8.1 dB Channel-to-Channel Matching 0.4 ≤ VGN ≤ 2.6 V 0.15 dB LOGIC LEVEL—HIGH/LOW, SHUTDOWN PREAMP, HLxx, SPxx, and ENxx pins and ENABLE INTERFACES Logic High 2.75 5 V Logic Low 0 1 V BIAS CURRENT—HIGH/LOW, ENABLE Logic High 80 μA Logic Low −12 μA INPUT RESISTANCE—HIGH/LOW, ENABLE 50 kΩ BIAS CURRENT— SHUTDOWN PREAMP Logic High 20 μA Logic Low 0 μA INPUT RESISTANCE—SHUTDOWN PREAMP 500 kΩ High/Low Response Time 0.6 μs Enable Response Time 100 μs POWER SUPPLY VPPx and VPVx pins Supply Voltage 4.5 5 5.5 V Quiescent Current Each channel—PrA and VGA enabled 19 mA Each channel—PrA disabled, VGA enabled 13 mA All channels enabled 76 mA Over Temperature −40°C < TA< +85°C 16 22.8 mA Quiescent Power Each channel—PrA and VGA enabled 95 mW Each channel—PrA disabled, VGA enabled 65 mW Disable Current All channels disabled 0.8 mA PSRR VGN = 0 V, all bypass capacitors removed, 1 MHz −60 dB Rev. B | Page 4 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION ENABLE SUMMARY PREAMP Noise VGA Optimizing the System Dynamic Range Attenuator Gain Control Output Stage VGA Noise APPLICATIONS INFORMATION ULTRASOUND BASIC CONNECTIONS PREAMP CONNECTIONS INPUT OVERDRIVE Input Overload Protection LOGIC INPUTS COMMON-MODE PINS DRIVING ADCs EVALUATION BOARD BOARD LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE