Datasheet ADRF6518 (Analog Devices) - 3

Data Sheet ADRF6518 SPECIFICATIONS
VPS, VPI, VPSD = 3.3 V, TA = 25°C, ZLOAD = 400 Ω, power mode bit (B9) = 0 (low power mode), digital gain code bits (B8 to B2) = 0000001, and dc offset disable bit (B1) = 0 (enabled), unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
FREQUENCY RESPONSE, FILTER BYPASS MODE ±1 dB Gain Flatness Bandwidth 300 MHz −3 dB Small Signal Bandwidth VGA2 and VGA3 21 dB digital gain setting 650 MHz VGA2 and VGA3 12 dB digital gain setting 1100 MHz FREQUENCY RESPONSE Low-Pass Corner Frequency, fC Six-pole Butterworth filter, 0.5 dB bandwidth 1 63 MHz Step Size 1 MHz Corner Frequency Absolute Accuracy Over operating temperature range ±8 % fC Corner Frequency Matching Channel A and Channel B at same gain and ±0.5 % fC bandwidth settings Pass-Band Ripple 0.5 dB p-p Gain Matching Channel A and Channel B at same gain and ±0.1 dB bandwidth settings Group Delay Variation From midband to peak Corner Frequency = 1 MHz 135 ns Corner Frequency = 30 MHz 11 ns Group Delay Matching Channel A and Channel B at same gain Corner Frequency = 1 MHz 5 ns Corner Frequency = 30 MHz 0.2 ns Stop-Band Rejection Relative to Pass Band 2 × fC 30 dB 5 × fC 75 dB INPUT STAGE INP1, INM1, INP2, INM2, VICM/AC Maximum Input Swing At minimum gain, VGN1 = 0 V 5.0 V p-p Differential Input Impedance 400 Ω Input Common-Mode Range, DC-Coupled 1.5 V p-p input voltage, HD3 > 65 dBc (VPI = 3.3 V), 1.35 1.95 V Mode VICM/AC floating or logic high 1.5 V p-p input voltage, HD3 > 65 dBc (VPI = 5.0 V), 1.35 3.1 V VICM/AC floating or logic high Input Common-Mode, AC-Coupled Mode VPI = 3.3 V to 5.0 V, VICM/AC = 0 V VPS/2 V VICM/AC Input Impedance 7.75 kΩ PEAK DETECTOR VPK, RAVG, SDO/RST Output Scaling Relative to differential peak voltage at filter 1 V/V peak input Reset Threshold Logic high duration > 25 ns >2.0 V GAIN CONTROL VGN1, VGN2, VGN3 Gain Range Maximum digital gains −6 +66 dB Minimum digital gains −36 +36 dB Voltage Attenuation Range Each attenuator; VGAIN from 0 V to 1 V −24 0 dB Gain Slope 30 mV/dB Gain Error VGAIN from 300 mV to 800 mV 0.2 dB Rev. A | Page 3 of 39 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS FILTER MODE BYPASS MODE MIXED POWER AND FILTER MODES CHARACTERIZATION NOISE FIGURE CALCULATION REGISTER MAP AND CODES THEORY OF OPERATION INPUT VGAs Driving ADRF6518 Single-Ended PEAK DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6518 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING PEAK DETECTOR CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EVM MEASUREMENT EVM SYSTEM MEASUREMENT EFFECT OF FILTER BW ON EVM PULL-DOWN RESISTORS FOR DISABLE FUNCTION INSTABILITY AT HIGH GAIN IN FILTER BYPASS MODE INSTABILITY AT LOW FILTER CORNERS AND LOW POWER MODE PEAK DETECTOR BANDWIDTH AND SLEW RATE LINEAR OPERATION OF THE ADRF6518 EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE