Datasheet ADRF6516 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 31 MHz, Dual Programmable Filters and Variable Gain Amplifiers |
| 页数 / 页 | 29 / 7 — Data Sheet. ADRF6516. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. NBL. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 1.1 Mb |
| 文件语言 | 英语 |
Data Sheet. ADRF6516. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. NBL. CMI. NPI. NMI. VPS. OFS. VPSD 1. 24 OPP1. COMD 2. 23 OPM1. LE 3. 22 COM
该数据表的模型线
文件文字版本
Data Sheet ADRF6516 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 1 1 M NBL CMI E NPI NMI VPS CO V OFS VPS 32 31 30 29 28 27 26 25 VPSD 1 24 OPP1 COMD 2 23 OPM1 LE 3 22 COM CLK 4 ADRF6516 21 GAIN DATA 5 TOP VIEW 20 VOCM SDO (Not to Scale) 6 19 COM COM 7 18 OPM2 VPS 8 17 OPP2 9 10 11 12 13 14 15 16 M 2 2 M S 2 CO NPI NMI VPS CO VPS OFD OFS NOTES
002
1. CONNECT THE EXPOSED PADDLE TO A LOW IMPEDANCE GROUND PAD.
09422- Figure 4. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 VPSD Digital Positive Supply Voltage: 3.15 V to 3.45 V. 2 COMD Digital Common. Connect to external circuit common using the lowest possible impedance. 3 LE Latch Enable. SPI programming pin. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 4 CLK SPI Port Clock. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 5 DATA SPI Data Input. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 6 SDO SPI Data Output. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 7, 9, 13, 19, 22, 28 COM Analog Common. Connect to external circuit common using the lowest possible impedance. 8, 12, 16, 25, 29 VPS Analog Positive Supply Voltage: 3.15 V to 3.45 V. 10, 11, 30, 31 INP2, INM2, Differential Inputs. 1600 Ω input impedance. INM1, INP1 14 OFDS Offset Compensation Loop Disable. Pull high to disable the offset compensation loop. 15, 26 OFS2, OFS1 Offset Compensation Loop Capacitors. Connect capacitors to circuit common. 17, 18, 23, 24 OPP2, OPM2, Differential Outputs. 30 Ω output impedance. Common-mode range is 0.7 V to 2.8 V; default is VPS/2. OPM1, OPP1 20 VOCM Output Common-Mode Setpoint. Defaults to VPS/2 if left floating. 21 GAIN Analog Gain Control. 0 V to 1 V, 15.5 mV/dB gain scaling. 27 VICM Input Common-Mode Voltage. VPS/2 V reference. Use to reference the optimal common-mode drive to the differential inputs. 32 ENBL Chip Enable. Pull high to enable. EP Exposed Paddle. Connect the exposed paddle to a low impedance ground pad. Rev. C | Page 7 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS REGISTER MAP AND CODES THEORY OF OPERATION INPUT BUFFERS PROGRAMMABLE FILTERS VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE FILTERS AND GAINS NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EFFECT OF FILTER BANDWIDTH ON EVM EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM EFFECT OF COFS VALUE ON EVM EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE
002
1. CONNECT THE EXPOSED PADDLE TO A LOW IMPEDANCE GROUND PAD.
09422- Figure 4. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 VPSD Digital Positive Supply Voltage: 3.15 V to 3.45 V. 2 COMD Digital Common. Connect to external circuit common using the lowest possible impedance. 3 LE Latch Enable. SPI programming pin. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 4 CLK SPI Port Clock. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 5 DATA SPI Data Input. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 6 SDO SPI Data Output. TTL levels: VLOW < 0.8 V, VHIGH > 2 V. 7, 9, 13, 19, 22, 28 COM Analog Common. Connect to external circuit common using the lowest possible impedance. 8, 12, 16, 25, 29 VPS Analog Positive Supply Voltage: 3.15 V to 3.45 V. 10, 11, 30, 31 INP2, INM2, Differential Inputs. 1600 Ω input impedance. INM1, INP1 14 OFDS Offset Compensation Loop Disable. Pull high to disable the offset compensation loop. 15, 26 OFS2, OFS1 Offset Compensation Loop Capacitors. Connect capacitors to circuit common. 17, 18, 23, 24 OPP2, OPM2, Differential Outputs. 30 Ω output impedance. Common-mode range is 0.7 V to 2.8 V; default is VPS/2. OPM1, OPP1 20 VOCM Output Common-Mode Setpoint. Defaults to VPS/2 if left floating. 21 GAIN Analog Gain Control. 0 V to 1 V, 15.5 mV/dB gain scaling. 27 VICM Input Common-Mode Voltage. VPS/2 V reference. Use to reference the optimal common-mode drive to the differential inputs. 32 ENBL Chip Enable. Pull high to enable. EP Exposed Paddle. Connect the exposed paddle to a low impedance ground pad. Rev. C | Page 7 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS REGISTER MAP AND CODES THEORY OF OPERATION INPUT BUFFERS PROGRAMMABLE FILTERS VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE FILTERS AND GAINS NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EFFECT OF FILTER BANDWIDTH ON EVM EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM EFFECT OF COFS VALUE ON EVM EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE