Datasheet ADRF6510 (Analog Devices) - 7
| 制造商 | Analog Devices |
| 描述 | 30 MHz Dual Programmable Filters and Variable Gain Amplifiers |
| 页数 / 页 | 32 / 7 — Data Sheet. ADRF6510. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. NI NI … |
| 修订版 | B |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
Data Sheet. ADRF6510. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. NI NI V C G O V. VPSD 1. 24 OPP1. COMD 2. 23 OPM1. LE 3. 22 COM. CLK 4
该数据表的模型线
文件文字版本
Data Sheet ADRF6510 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS L W 1 B 1 1 S M S S S N P M P O N F P E NI NI V C G O V 32 31 30 29 28 27 26 25 VPSD 1 24 OPP1 COMD 2 23 OPM1 LE 3 22 COM ADRF6510 CLK 4 21 GAIN DATA 5 TOP VIEW 20 VOCM (Not to Scale) SDO 6 19 COM COM 7 18 OPM2 VPS 8 17 OPP2 9 10 11 12 13 14 15 16 M 2 2 S M S 2 S O P M P O D S P C NI N F I V C F V O O
02
NOTES
0
1. CONNECT THE EXPOSED PADDLE TO
002-
A LOW IMPEDANCE GROUND PAD.
09 Figure 4. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 VPSD Digital Positive Supply Voltage: 4.75 V to 5.25 V. 2 COMD Digital Common. Connect to external circuit common using the lowest possible impedance. 3 LE Latch Enable. SPI programming pin. CMOS levels: VLOW < 0.8 V, VHIGH > 2 V. 4 CLK SPI Port Clock. CMOS levels: VLOW < 0.8 V, VHIGH > 2 V. 5 DATA SPI Data Input. CMOS levels: VLOW < 0.8 V, VHIGH > 2 V. 6 SDO SPI Data Output. CMOS levels: VLOW < 0.8 V, VHIGH > 2 V. 7, 9, 13, 19, 22, 28 COM Analog Common. Connect to external circuit common. 8, 12, 16, 25, 29 VPS Analog Positive Supply Voltage: 4.75 V to 5.25 V. 10, 11, 30, 31 INP2, INM2, Differential Inputs. 400 Ω input impedance. Common-mode range is 1.5 V to 2.5 V; default is 2.1 V. INM1, INP1 14 OFDS Offset Correction Loop Disable. Pull high to disable the offset correction loop. 15, 26 OFS2, OFS1 Offset Correction Loop Compensation Capacitors. Connect capacitors to circuit common. 17, 18, 23, 24 OPP2, OPM2, Differential Outputs. 20 Ω output impedance. Common-mode range is 1.5 V to 3 V; default is VPS/2. OPM1, OPP1 20 VOCM Output Common-Mode Setpoint. Defaults to VPS/2 if left open. 21 GAIN Analog Gain Control. 0 V to 2 V, 30 mV/dB gain scaling. 27 GNSW Front-End Gain Switch, 6 dB or 12 dB. Pull low for 6 dB; pull high for 12 dB. 32 ENBL Chip Enable. Pull high to enable. EP Exposed Paddle. Connect the exposed paddle to a low impedance ground pad. Rev. B | Page 7 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT BUFFERS PROGRAMMABLE FILTERS VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE FILTERS NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM EFFECT OF FILTER BANDWIDTH ON EVM EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM EFFECT OF COFS ON EVM ANTI-ALIASING FILTER EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS USB Section Configuration Options OUTLINE DIMENSIONS ORDERING GUIDE
02
NOTES
0
1. CONNECT THE EXPOSED PADDLE TO
002-
A LOW IMPEDANCE GROUND PAD.
09 Figure 4. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 VPSD Digital Positive Supply Voltage: 4.75 V to 5.25 V. 2 COMD Digital Common. Connect to external circuit common using the lowest possible impedance. 3 LE Latch Enable. SPI programming pin. CMOS levels: VLOW < 0.8 V, VHIGH > 2 V. 4 CLK SPI Port Clock. CMOS levels: VLOW < 0.8 V, VHIGH > 2 V. 5 DATA SPI Data Input. CMOS levels: VLOW < 0.8 V, VHIGH > 2 V. 6 SDO SPI Data Output. CMOS levels: VLOW < 0.8 V, VHIGH > 2 V. 7, 9, 13, 19, 22, 28 COM Analog Common. Connect to external circuit common. 8, 12, 16, 25, 29 VPS Analog Positive Supply Voltage: 4.75 V to 5.25 V. 10, 11, 30, 31 INP2, INM2, Differential Inputs. 400 Ω input impedance. Common-mode range is 1.5 V to 2.5 V; default is 2.1 V. INM1, INP1 14 OFDS Offset Correction Loop Disable. Pull high to disable the offset correction loop. 15, 26 OFS2, OFS1 Offset Correction Loop Compensation Capacitors. Connect capacitors to circuit common. 17, 18, 23, 24 OPP2, OPM2, Differential Outputs. 20 Ω output impedance. Common-mode range is 1.5 V to 3 V; default is VPS/2. OPM1, OPP1 20 VOCM Output Common-Mode Setpoint. Defaults to VPS/2 if left open. 21 GAIN Analog Gain Control. 0 V to 2 V, 30 mV/dB gain scaling. 27 GNSW Front-End Gain Switch, 6 dB or 12 dB. Pull low for 6 dB; pull high for 12 dB. 32 ENBL Chip Enable. Pull high to enable. EP Exposed Paddle. Connect the exposed paddle to a low impedance ground pad. Rev. B | Page 7 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT BUFFERS PROGRAMMABLE FILTERS VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE FILTERS NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM EFFECT OF FILTER BANDWIDTH ON EVM EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM EFFECT OF COFS ON EVM ANTI-ALIASING FILTER EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS USB Section Configuration Options OUTLINE DIMENSIONS ORDERING GUIDE