Datasheet ADL5201 (Analog Devices) - 4

ADL5201 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
POWER-UP INTERFACE PWUP pin Power-Up Threshold Minimum voltage to enable the device 1.4 V Maximum voltage to enable the device 3.3 V PWUP Input Bias Current 1 μA GAIN CONTROL INTERFACE VIH Minimum/maximum voltage for a logic high 1.41 3.3 V VIL Maximum voltage for a logic low 0.8 Maximum Input Bias Current 1 μA SPI TIMING LATCH, SCLK, SDIO, data pins fSCLK 1/tSCLK 20 MHz tDH Data hold time 5 ns tDS Data setup time 5 ns tPW SCLK high pulse width 5 ns POWER INTERFACE Supply Voltage 4.5 5.5 V Quiescent Current High performance mode 110 mA 85°C 120 mA Low power mode 80 mA 85°C 95 mA Power-Down Current PWUP low 7 mA 1 The minimum value for a logic high on the PM pin is 2.8 V.
TIMING DIAGRAMS tSCLK tPW SCLK tDH tDS CS tDS tDH
002
SDIO DNC DNC DNC DNC DNC DNC DNC R/W FA1 FA0 D5 D4 D3 D2 D1 D0
09388- Figure 2. SPI Interface Read/Write Mode Timing Diagram
tDS tDS UPDN_DAT tPW UPDN_CLK UP DN RESET
003
tDS tDH
09388- Figure 3. Up/Down Mode Timing Diagram
LATCH A5 TO A0
104 8-
tDH
0938 Figure 4. Parallel Mode Timing Diagram Rev. C | Page 4 of 26 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack UP/DOWN INTERFACE Truth Table LOGIC TIMING CIRCUIT DESCRIPTION BASIC STRUCTURE INPUT SYSTEM OUTPUT AMPLIFIER GAIN CONTROL APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LAYOUT CONSIDERATIONS EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Configuration Options for the USB Section OUTLINE DIMENSIONS ORDERING GUIDE