Datasheet ADL5240 (Analog Devices)

100 MHz to 4000 MHz RF/IF Digitally Controlled VGA Data Sheet ADL5240 FEATURES GENERAL DESCRIPTION Operating frequency from 100 MHz to 4000 MHz
The ADL5240 is a high performance, digital y control ed variable
Digitally controlled VGA with serial and parallel interfaces
gain amplifier (VGA) operating from 100 MHz to 4000 MHz.
6-bit, 0.5 dB digital step attenuator
The VGA integrates a high performance, 20 dB gain, internal y
31.5 dB gain control range with ±0.25 dB step accuracy
matched amplifier (AMP) with a 6-bit digital step attenuator
Gain block amplifier specifications
(DSA) that has a gain control range of 31.5 dB in 0.5 dB steps
Gain: 19.7 dB at 2.14 GHz
with ±0.25 dB step accuracy. The attenuation of the DSA can be
OIP3: 41.0 dBm at 2.14 GHz
controlled using a serial or parallel interface.
P1dB: 19.5 dBm at 2.14 GHz
Both the gain block and DSA are internal y matched to 50 Ω at
Noise figure: 2.9 dB at 2.14 GHz
their inputs and outputs and are separately biased. The separate
Gain block or digital step attenuator can be first
bias allows all or part of the ADL5240 to be used, which facilitates
Single supply operation from 4.75 V to 5.25 V
easy reuse throughout a design. The pinout of the ADL5240 also
Low quiescent current of 93 mA
enables either the gain block or DSA to be first, giving the VGA
Thermally efficient, 5 mm × 5 mm, 32-lead LFCSP
maximum flexibility in a signal chain.
The companion ADL5243 integrates a ¼ W driver amplifier to the output of the gain block and DSA
The ADL5240 consumes just 93 mA and operates from a single supply ranging from 4.75 V to 5.25 V. The VGA is packaged in a
APPLICATIONS
thermal y efficient, 5 mm × 5 mm, 32-lead LFCSP and is fully
Wireless infrastructure
specified for operation from −40°C to +85°C. A ful y populated
Automated test equipment
evaluation board is available.
RF/IF gain control FUNCTIONAL BLOCK DIAGRAM A K E CL DAT L SEL D0/ D1/ D2/ D3 D4 D5 D6 32 31 30 29 28 27 26 25 VDD 1 24 VDD SERIAL/PARALLEL INTERFACE NC 2 23 NC NC 3 22 NC DSAIN 4 21 DSAOUT 0.5dB 1dB 2dB 4dB 8dB 16dB NC 5 20 NC NC 6 19 NC ADL5240 AMP NC 7 18 NC NC 8 17 NC 9 10 11 12 13 14 15 16 N NC CC NC NC NC NC NC /V MPI A UT O
001
P AM
09430- Figure 1.
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Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Applications Information Basic Layout Connections Amplifier Bias Digital Step Attenuator Bias Amplifier RF Input Interface Amplifier RF Output Interface DSA RF Input Interface DSA RF Output Interface DSA SPI Interface SPI Timing SPI Timing Sequence Loop Performance Amplifier Drive Level for Optimum ACLR Thermal Considerations Evaluation Board Outline Dimensions Ordering Guide