Datasheet HMC628LP4, 628LP4E (Analog Devices) - 9

制造商Analog Devices
描述BiCMOS 5-Bit Digital Variable Gain Amp. SMT, 50 - 800 MHz
页数 / 页14 / 9 — HMC628LP4 / 628LP4E. BiCMOS MMIC 5-Bit DIGITAL. VARIABLE GAIN AMPLIFIER, …
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HMC628LP4 / 628LP4E. BiCMOS MMIC 5-Bit DIGITAL. VARIABLE GAIN AMPLIFIER, 50 - 800 MHz. Power-Up States. PUP Truth Table

HMC628LP4 / 628LP4E BiCMOS MMIC 5-Bit DIGITAL VARIABLE GAIN AMPLIFIER, 50 - 800 MHz Power-Up States PUP Truth Table

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HMC628LP4 / 628LP4E
v07.0410
BiCMOS MMIC 5-Bit DIGITAL VARIABLE GAIN AMPLIFIER, 50 - 800 MHz Power-Up States PUP Truth Table
If LE is set to logic LOW at power-up, the logic state of Gain Relative to LE PUP1 PUP2 PUP1 and PUP2 determines the power-up state of the Maximum Gain part per PUP truth table. If the LE is set to logic HIGH 0 0 0 Insertion Loss at power-up, the logic state of B4-B0 determines the 0 1 0 -8 power-up state of the part per truth table. The DVGA 0 0 1 -16 latches in the desired power-up state approximately 0 1 1 -23 200 ms after power-up. 1 X X 0 to -23 dB Note: Power-Up with LE= 1 provides direct parallel operation with B4-B0.
Power-On Sequence
The ideal power-up sequence is: GND, Vdd, digital inputs, RF inputs. The relative order of the digital 12 inputs are not important as long as they are powered after Vdd / GND
Truth Table
ATTENUATION T
Absolute Maximum Ratings
B4[1] B3[1] B2 B1 B0 (dB) RF Input Power 20 dBm 0 0 0 0 0 0 RF Output Power 22 dBm 1 0 0 0 0 1 2 0 0 0 1 0 Digital Inputs (B0-B4, Shift Clock, -0.5V to Vdd +0.5V L - SM Latch Enable & Data Input) 3 0 0 0 1 1 A Bias Voltage (Vdd) 5.6 V 4 0 0 1 0 0 5 0 0 1 0 1 IT Junction Temperature 125 °C 6 0 0 1 1 0 Continuous Pdiss (T = 85 °C) IG 0.54 W (derate 13.5 mW/°C above 85 °C) [1] 7 0 0 1 1 1 Thermal Resistance 8 0 1 0 0 0 74.3 °C/W (Junction to ground paddle) - D 9 0 1 0 0 1 Storage Temperature -65 to +150 °C S 10 0 1 0 1 0 R Operating Temperature -40 to +85 °C 11 0 1 0 1 1 12 0 1 1 0 0 IE 13 0 1 1 0 1 IF
Bias Voltage
14 0 1 1 1 0 L 15 0 1 1 1 1 P Vdd (V) Idd (Typ.) (mA) 16 1 X 0 0 0 M 5V 65 17 1 X 0 0 1 A 18 1 X 0 1 0
Control Voltage Table
19 1 X 0 1 1 IN 20 1 X 1 0 0 State Vdd = +3V Vdd = +5V A 21 1 X 1 0 1 Low 0 to 0.5V @ <1 μA 0 to 0.8V @ <1 μA G 22 1 X 1 1 0 High 2 to 3V @ <1 μA 2 to 5V @ <1 μA E 23 1 X 1 1 1 L [1] Enabling B4 disables B3, the minimum attenuation is 16 dB B IA ELECTROSTATIC SENSITIVE DEVICE R OBSERVE HANDLING PRECAUTIONS A V Inf F or o m r pr ation ifc ur e, de nished lbiv y e Anry alo a g n D d to p evices is la beclie o eved rde to b r e sa: H ccur iattti e tae M nd reliicr abl ow e. H a o v wee C ver, o n rp o o F roar tiporin c ,e 2 , 0 de A liv lepha R ry, an o d t ad, C o plac h e eolm rdesrfo s: rd, MA 01 Analog Devi 8 c 2 e 4 s, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No
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