Datasheet VIPER26K (STMicroelectronics) - 5

VIPer26K Electrical and thermal ratings 2 Electrical and thermal ratings Table 2. Absolute maximum ratings Value Symbol Pin Parameter(1),(2) Unit Min. Max.
VDRAIN 13-16 Drain-to-source (ground) voltage 1.05 KV Pulse drain current (limited by IDRAIN 3 A TJ = 150 °C) V Internally DD 5 Supply voltage -0.3 V limited IDD 5 Input current 20 mA VFB 7 Feedback pin voltage -0.3 4.8 V VCOMP 8 Input pin voltage -0.3 3.5 V PTOT Power dissipation at TA < 60 °C 1.05(3) W TJ Operating junction temperature range -40 150 °C TSTG Storage temperature -55 150 °C 1. Stresses beyond those listed absolute maximum ratings may cause permanent damage to the device. 2. Exposure to absolute-maximum-rated conditions for extended periods may affect the device reliability. 3. When mounted on a standard single side FR4 board with 100 mm² (0.1552 inch) of Cu (35 μm thick).
Table 3. Thermal data Symbol Parameter Max. value Unit
R Thermal resistance junction to case (1) TH-JC 10 °C/W (Dissipated power = 1 W) R Thermal resistance junction to case (2) TH-JC 5 °C/W (Dissipated power = 1 W) R Thermal resistance junction ambient (1) TH-JA 120 °C/W (Dissipated power = 1 W) R Thermal resistance junction ambient (2) TH-JA 85 °C/W (Dissipated power = 1 W) 1. When mounted on a standard, single side FR4 board with minimum copper area. 2. When mounted on a standard, single side FR4 board with 100 mm2 of Cu (35 μm thick). DS12978 Rev 1 5/28 28 Document Outline Figure 1. Basic application schematic 1 Pin setting Figure 2. Connection diagram Table 1. Pin description 2 Electrical and thermal ratings Table 2. Absolute maximum ratings Table 3. Thermal data Figure 3. RthJA Table 4. Avalanche characteristics 3 Electrical characteristics Table 5. Power section Table 6. Supply section Table 7. Controller section 3.1 Typical electrical characteristics Figure 4. IDLIM vs. Tj Figure 5. FOSC vs. Tj Figure 6. VHV_START vs. Tj Figure 7. VREF_FB vs. Tj Figure 8. IDD0 vs. Tj Figure 9. IDD1 vs. Tj Figure 10. GM vs. Tj Figure 11. HCOMP vs. Tj Figure 12. ICOMP(source/sink) vs. Tj Figure 13. ICOMP(max source) vs. Tj Figure 14. Power MOSFET capacitances variation vs. VDS @ VGS=0, f=1MHz Figure 15. VBVDSS vs. TJ .. Figure 16. RDS(on) vs. Tj Figure 17. Maximum avalanche energy vs. Tj Figure 18. SOA SSOP10 package 4 General description 4.1 Block diagram Figure 19. Block diagram 4.2 Typical power capability Table 8. Typical power 4.3 Primary MOSFET 4.4 High voltage startup Figure 20. Timing diagram: normal power-up and power-down sequences 4.5 Oscillator 4.6 Soft-start 4.7 Current limit set point 4.8 FB pin and COMP pin Figure 21. Feedback circuit Figure 22. COMP pin vs. IDLIM 4.9 Burst mode Figure 23. Load-dependent operating modes: timing diagram 4.10 Automatic auto restart after overload or short-circuit Figure 24. Timing diagram: OLP sequence 4.11 Open loop failure protection 4.12 Thermal shutdown Figure 25. Timing diagram: OLP sequence 5 Application information Figure 26. Typical isolated flyback configuration with secondary regulation Figure 27. Typical isolated flyback configuration with primary regulation Figure 28. Typical non isolated flyback configuration Figure 29. Ultra wide range Buck configuration 5.1 Layout guidelines and design recommendations Figure 30. Recommended routing for flyback converter Figure 31. Recommended routing for Buck converter 6 Package information 6.1 SO16N package information Figure 32. SO16N package outline Table 9. SO16N mechanical data 7 Order code Table 10. Order codes 8 Revision history Table 11. Document history