Datasheet VIPER26K (STMicroelectronics) - 8

Electrical characteristics VIPER26K Table 6. Supply section (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit
V V DDon internal high voltage DDCSon 9.5 10.5 11.5 V current generator threshold V V DD under voltage shutdown DDoff 7 8 9 V threshold Operating supply current, F I OSC = 0 kHz, DD0 0.6 mA not switching VCOMP = GND Operating supply current, V I DRAIN = 120 V, DD1 2 mA switching FOSC = 60 kHz Operating supply current IDDoff V with VDD < VDDoff DD < VDDoff 0.35 mA Open loop failure current V I DD = VDDclamp DDol 4 mA threshold VCOMP = 3.3 V
Table 7. Controller section Symbol Parameter Test conditions Min. Typ. Max. Unit E/A
VREF_FB Input voltage 3.2 3.3 3.4 V IFB_PULL UP Pull-up current -1 μA GM Transconductance 2 mA/V
Compensation pin (Comp)
VCOMPH Upper saturation limit TJ = 25°C 3 V VCOMPL Burst mode threshold TJ = 25°C 1 1.1 1.2 V VHYS Burst mode hysteresis 40 mV HCOMP ΔVCOMP/ΔIDRAIN TJ = 25°C 1.9 2.35 2.8 V/A RCOMP(DYN) Dynamic resistance VFB = GND 15 kΩ Source / sink Current VFB > 100mV 150 μA ICOMP V Max. source current COMP = GND, 220 μA VFB = GND 8/28 DS12978 Rev 1 Document Outline Figure 1. Basic application schematic 1 Pin setting Figure 2. Connection diagram Table 1. Pin description 2 Electrical and thermal ratings Table 2. Absolute maximum ratings Table 3. Thermal data Figure 3. RthJA Table 4. Avalanche characteristics 3 Electrical characteristics Table 5. Power section Table 6. Supply section Table 7. Controller section 3.1 Typical electrical characteristics Figure 4. IDLIM vs. Tj Figure 5. FOSC vs. Tj Figure 6. VHV_START vs. Tj Figure 7. VREF_FB vs. Tj Figure 8. IDD0 vs. Tj Figure 9. IDD1 vs. Tj Figure 10. GM vs. Tj Figure 11. HCOMP vs. Tj Figure 12. ICOMP(source/sink) vs. Tj Figure 13. ICOMP(max source) vs. Tj Figure 14. Power MOSFET capacitances variation vs. VDS @ VGS=0, f=1MHz Figure 15. VBVDSS vs. TJ .. Figure 16. RDS(on) vs. Tj Figure 17. Maximum avalanche energy vs. Tj Figure 18. SOA SSOP10 package 4 General description 4.1 Block diagram Figure 19. Block diagram 4.2 Typical power capability Table 8. Typical power 4.3 Primary MOSFET 4.4 High voltage startup Figure 20. Timing diagram: normal power-up and power-down sequences 4.5 Oscillator 4.6 Soft-start 4.7 Current limit set point 4.8 FB pin and COMP pin Figure 21. Feedback circuit Figure 22. COMP pin vs. IDLIM 4.9 Burst mode Figure 23. Load-dependent operating modes: timing diagram 4.10 Automatic auto restart after overload or short-circuit Figure 24. Timing diagram: OLP sequence 4.11 Open loop failure protection 4.12 Thermal shutdown Figure 25. Timing diagram: OLP sequence 5 Application information Figure 26. Typical isolated flyback configuration with secondary regulation Figure 27. Typical isolated flyback configuration with primary regulation Figure 28. Typical non isolated flyback configuration Figure 29. Ultra wide range Buck configuration 5.1 Layout guidelines and design recommendations Figure 30. Recommended routing for flyback converter Figure 31. Recommended routing for Buck converter 6 Package information 6.1 SO16N package information Figure 32. SO16N package outline Table 9. SO16N mechanical data 7 Order code Table 10. Order codes 8 Revision history Table 11. Document history