Datasheet RX65N, RX651 Groups (Renesas) - 2

link to page 2 link to page 12 link to page 2 link to page 12 RX65N Group, RX651 Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different packages. Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the modules differ depending on the number of pins on the package and the capacity of the code flash memory. For details, see Table 1.2, Code Flash Memory Capacity and Comparison of Functions for Different Packages.
Table 1.1 Outline of Specifications (1/10) Classification Module/Function Description
CPU CPU Maximum operating frequency: 120 MHz 32-bit RX CPU (RXv2) Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers Basic instructions: 75 Floating-point instructions: 11 DSP instructions: 23 Addressing modes: 11 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 × 32 → 64 bits On-chip divider: 32 / 32 → 32 bits Barrel shifter: 32 bits FPU Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard Memory Code flash memory Capacity: 512 Kbytes/768 Kbytes/1 Mbyte/1.5 Mbytes/2 Mbytes 50 MHz  No-wait cycle access 100 MHz  1-wait cycle access 100 MHz  2-wait cycle access Instructions hitting the ROM cache or operand = 120 MHz: No-wait access On-board programming: Four types Off-board programming (parallel programmer mode) Instructions are executable only for the program stored in the TM target area by using the Trusted Memory (TM) function and protection against data reading is realized. A dual-bank structure allows programming during reading or exchanging the start-up areas Data flash memory Capacity: 32 Kbytes Programming/erasing: 100,000 times Unique ID 16-byte unique ID for the device RAM Capacity: 256 Kbytes (Products with 1 Mbyte of code flash memory or less) RAM: 256 Kbytes Capacity: 640 Kbytes (Products with at least 1.5 Mbytes of code flash memory) RAM: 256 Kbytes Expansion RAM: 384 Kbytes 120 MHz, no-wait access Standby RAM Capacity: 8 Kbytes Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access R01DS0276EJ0230 Rev.2.30 Page 2 of 246 Jun 20, 2019 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 2. CPU 2.1 General-Purpose Registers (R0 to R15) 2.2 Control Registers 2.3 Accumulator 3. Address Space 3.1 Address Space 3.2 External Address Space 4. I/O Registers 4.1 I/O Register Addresses (Address Order) 5. Electrical Characteristics 5.1 Absolute Maximum Ratings 5.2 DC Characteristics 5.3 AC Characteristics 5.3.1 Reset Timing 5.3.2 Clock Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes 5.3.4 Control Signal Timing 5.3.5 Bus Timing 5.3.6 EXDMAC Timing 5.3.7 Timing of On-Chip Peripheral Modules 5.4 USB Characteristics 5.5 A/D Conversion Characteristics 5.6 D/A Conversion Characteristics 5.7 Temperature Sensor Characteristics 5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 5.9 Oscillation Stop Detection Timing 5.10 Battery Backup Function Characteristics 5.11 Flash Memory Characteristics 5.12 Boundary Scan Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice