Datasheet 5X2503 (IDT) - 4

5X2503 Datasheet
Figure 2. DFC Function Block Diagram
M M di di vi vi der der PLL2 PLL2 OUT DIV OUT DIV Selector Selector 00 N divider 00 N divider 01 N divider 01 N divider 10 N divider 10 N divider 11 N divider 11 N divider DFC1:0 DFC1:0 OTP/I2C OTP/I2C
Table 2. DFC Function Priority DFC_EN bit DFC Mode OE Pins (W32[4]) OE1_fun_sel I2C Pins SCL_DFC1 SDA_DFCO DFC[1:0] Notes
Active (SCL = Off OE In* 0 00 or 01 or 10* SCL Input SDA I/O N/A DFC disable 1 at POR) One pin DFC On DFC0 In 1 11 Active SCL Input SDA I/O DFC0 = OE via OE1 I2C pin as Inactive (SCL DFC1 = On OE In* 1 00 or 01 or 10* DFC1 DFC0 DFC control = 0 at POR) SCL_DFC1 pins Active (SCL = I2C control On OE In* 1 00 or 01 or 10* SCL Input SDA I/O W30[1:0] 1 at POR) DFC mode * See OE Pin Function table.
DFC Function Programming
▪ Register B63b3:2 selects DFC00–DFC11 configuration. ▪ Byte16–19 are the registers for PLL2 VCO setting, based on B63b3:2 configuration selection, the data write to B16–19 will be stored in selected configuration OTP memory. ▪ Refer to DFC Function Priority table. Select proper control pin(s) to activate DFC function. ▪ Note the DFC function can also be controlled by I2C access.
PPS – Proactive Power Saving Function
PPS (Proactive Power Saving) is an IDT patented unique design for the clock generator that proactively detects end device power down state and then switches output clocks between normal operation clock frequency and low power mode 32kHz clock that only consumes < 5μA current. The system could save power when the device goes into power down or sleep mode. The PPS function diagram is shown as below. ©2017 Integrated Device Technology, Inc 4 December 18, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Power Group Output Source Selection Register Setting Tables Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN Package Pin Descriptions Table 1. Pin Descriptions Device Feature and Function DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 2. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 3. OE1 Pin Function Table Table 4. SDA/SCL Function Selection Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 5. Output Divider 1 Table 6. Output Divider 2, 3, and 5 Table 7. Output Divider 4 Output Clock Test Conditions Figure 5. LVCMOS Output Clock Test Condition Absolute Maximum Ratings Table 8. Absolute Maximum Ratings Recommended Operating Conditions Table 9. Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 10. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Integrated Crystal Characteristics Table 11. Crystal Characteristics DC Electrical Characteristics Table 12. DC Electrical Characteristics 1,2 Electrical Characteristics–Input Parameters Table 13. Electrical Characteristics–Input Parameters 1 DC Electrical Characteristics for 1.8V LVCMOS Table 14. DC Electrical Characteristics – 1.8V LVCMOS AC Electrical Characteristics Table 15. AC Timing Electrical Characteristics – 32.768kHz Table 16. AC Timing Electrical Characteristics – 1.8V Table 17. AC Timing Electrical Characteristics, 1.2V / 1.8V I2C Bus DC Characteristics Table 18. I2C Bus DC Characteristics Table 19. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 20. Spread Spectrum Generation Specifications General SMBus Serial Interface Information Package Outline Drawings Figure 6. NDG12 Package Drawing – page 1 Figure 7. NDG12 Package Drawing – page 2 Ordering Information Marking Diagram Revision History