Datasheet 5X2503 (IDT) - 6

5X2503 Datasheet SCL/SDA are also multiple function pins. The two pins can be configured as output enable control (OE), or I2C interface or Dynamic Frequency Control (DFC) functions by programming and hardware pin latch.
Table 3. OE1 Pin Function Table Byte30 Function bit6 bit5
OUT1 Output Enable/Disable 0 0 Global Power Down (PD#) 0 1 OUT1 Proactive Power Saving Input (OUT1 PPS) 1 0 DFC0 1 1
Table 4. SDA/SCL Function Selection SEL_DFC (latched) Enable OE2/3 B36<2> DFC_EN B32<4> OE1 Funsel B30<6:5> Function of SCL/SDA
0 0 0 00, 01, 10 NA 0 0 1 00, 01, 10 SCL = DFC1, SDA = DFC0 0 1 X 00, 01, 10 SCL = OE3, SDA = OE2 1 X X 00, 01, 10 SCL, SDA
Spread Spectrum
The 5X2503 supports spread spectrum clocks from PLL1. PLL1 has built-in analog spread spectrum; PLL2 and PLL3 use seed clock from PLL1.
ORT – VCO Overshoot Reduction Technology
The 5X2503 supports innovate the VCO overshoot reduction technology to prevent the output clock frequency spike when the device is change frequency on the fly or doing DFC (Dynamic Frequency Control) function. The VCO frequency change are under control instead of free run to targeted frequency.
PLL Features and Descriptions Table 5. Output Divider 1 Output Divider Bits [3:2] Output Divider Bits [1:0] 00 01 10 11
00 1 2 4 8 01 4 8 16 32 10 5 10 20 40 11 6 12 24 48 ©2017 Integrated Device Technology, Inc 6 December 18, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Power Group Output Source Selection Register Setting Tables Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN Package Pin Descriptions Table 1. Pin Descriptions Device Feature and Function DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 2. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 3. OE1 Pin Function Table Table 4. SDA/SCL Function Selection Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 5. Output Divider 1 Table 6. Output Divider 2, 3, and 5 Table 7. Output Divider 4 Output Clock Test Conditions Figure 5. LVCMOS Output Clock Test Condition Absolute Maximum Ratings Table 8. Absolute Maximum Ratings Recommended Operating Conditions Table 9. Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 10. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Integrated Crystal Characteristics Table 11. Crystal Characteristics DC Electrical Characteristics Table 12. DC Electrical Characteristics 1,2 Electrical Characteristics–Input Parameters Table 13. Electrical Characteristics–Input Parameters 1 DC Electrical Characteristics for 1.8V LVCMOS Table 14. DC Electrical Characteristics – 1.8V LVCMOS AC Electrical Characteristics Table 15. AC Timing Electrical Characteristics – 32.768kHz Table 16. AC Timing Electrical Characteristics – 1.8V Table 17. AC Timing Electrical Characteristics, 1.2V / 1.8V I2C Bus DC Characteristics Table 18. I2C Bus DC Characteristics Table 19. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 20. Spread Spectrum Generation Specifications General SMBus Serial Interface Information Package Outline Drawings Figure 6. NDG12 Package Drawing – page 1 Figure 7. NDG12 Package Drawing – page 2 Ordering Information Marking Diagram Revision History