Datasheet 5X2503 (IDT) - 9

制造商IDT
描述MicroClock Programmable Clock Generator with Embedded Crystal
页数 / 页30 / 9 — Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down. …
修订版20171218
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Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down. Resistance

Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance

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5X2503 Datasheet
Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance
(TA = +25 °C)
Table 10. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Symbol Parameter Minimum Typical Maximum Units
CIN Input Capacitance (OE, SDA, SCL) — 3 7 pF Pul -down Resistor OE — 150 — kΩ ROUT LVCMOS Output Driver Impedance (VDDOUTx = 1.8V) — 17 — Ω
Integrated Crystal Characteristics Table 11. Crystal Characteristics Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation — Fundamental Frequency — — 26 — MHz Frequency Tolerance (25°C)1 — -20 — 20 ppm Equivalent Series Resistance (ESR) — — 10 100 Ω Shunt Capacitance — — 2 7 pF Load Capacitance (CL) — 6 8 10 pF Maximum Crystal Drive Level — — — 100 μW 1 Frequency deviation–refer to center frequency.
DC Electrical Characteristics Table 12. DC Electrical Characteristics 1,2 Symbol Parameter Conditions Minimum Typical Maximum Units
VDD = VDDOUTx = VDD1_8 = 1.8V; OUT1 = 12MHz, — 2.0 — mA OUT3 = 26MHz, OUT2 off, no load. VDD = VDDOUTx = VDD1_8 = 1.8V; OUT1 = 12MHz, — 3.5 — mA OUT3 = 26MHz, OUT2 off, with load. IDD Operation Supply Current VDD = VDDOUTx = VDD1_8 = 1.8V; OUT1 = 26MHz, — 1.8 — mA OUT3 = 26MHz, OUT2 = 32kHz, no load. VDD = VDDOUTx = VDD1_8 = 1.8V; OUT1 = 26MHz, — 3.8 — mA OUT3 = 26MHz, OUT2 = 32kHz, with load. PD asserted with V I DD1_8 and VDDOUTx on, I2C DDPD Power Down Current — 390 — μA programming, 32kHz running. V I DDOUT2 off and only VDDOUT1 and VDD1_8 on, DDSUSPEND Power Suspend Current — 1.6 2.0 μA I2C programming, 32kHz running. 1 Single CMOS driver active. 2 OUT1–3 current measured with 0.5 inches transmission line and no load. ©2017 Integrated Device Technology, Inc 9 December 18, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Power Group Output Source Selection Register Setting Tables Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN Package Pin Descriptions Table 1. Pin Descriptions Device Feature and Function DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 2. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 3. OE1 Pin Function Table Table 4. SDA/SCL Function Selection Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 5. Output Divider 1 Table 6. Output Divider 2, 3, and 5 Table 7. Output Divider 4 Output Clock Test Conditions Figure 5. LVCMOS Output Clock Test Condition Absolute Maximum Ratings Table 8. Absolute Maximum Ratings Recommended Operating Conditions Table 9. Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 10. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Integrated Crystal Characteristics Table 11. Crystal Characteristics DC Electrical Characteristics Table 12. DC Electrical Characteristics 1,2 Electrical Characteristics–Input Parameters Table 13. Electrical Characteristics–Input Parameters 1 DC Electrical Characteristics for 1.8V LVCMOS Table 14. DC Electrical Characteristics – 1.8V LVCMOS AC Electrical Characteristics Table 15. AC Timing Electrical Characteristics – 32.768kHz Table 16. AC Timing Electrical Characteristics – 1.8V Table 17. AC Timing Electrical Characteristics, 1.2V / 1.8V I2C Bus DC Characteristics Table 18. I2C Bus DC Characteristics Table 19. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 20. Spread Spectrum Generation Specifications General SMBus Serial Interface Information Package Outline Drawings Figure 6. NDG12 Package Drawing – page 1 Figure 7. NDG12 Package Drawing – page 2 Ordering Information Marking Diagram Revision History