Datasheet 5L2503 (IDT) - 4

5L2503 Datasheet
Device Features and Functions DFC – Dynamic Frequency Control
▪ OTP programmable–4 different feedback fractional dividers (4 VCO frequencies) that apply to PLL2. ▪ ORT (overshoot reduction) function will be applied automatical y during the VCO frequency change. ▪ Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection.
Figure 2. DFC Function Block Diagram
M divider PLL2 OUT DIV Selector 00 N divider 01 N divider 10 N divider 11 N divider DFC1:0 OTP/I2C
Table 7. DFC Function Priority DFC Mode OE Pin DFC_EN bit (W32[4]) OE1_fun_sel I2C Pins SCL_DFC1 SDA_DFC0 DFC[1:0] Notes
Active (SCL = Not Off OE In * 0 00 or 01 or 10 * SCL input SDA I/O DFC disable 1 at POR) applicable One pin DFC On DFC0 In 1 11 Active SCL input SDA I/O DFC0 = OE via OE1 Inactive (SCL= DFC1 = I2C pin as DFC On OE In * 1 00 or 01 or 10 * DFC1 DFC0 0 at POR) SCL_DFC1 control pins Active (SCL = I2C control On OE In * 1 00 or 01 or 10 * SCL input SDA I/O W30[1:0] 1 at POR) DFC mode * See OE Pin Function table.
DFC Function Programming
▪ Register B63b3:2 select DFC00–DFC11 configuration. ▪ Byte16–19 are the register for PLL2 VCO setting. Based on B63b3:2 configuration selection, the data write to B16–19 will be stored in selected configuration OTP memory. ▪ Refer to DFC Function Priority table; select proper control pin(s) to activate DFC function. ▪ Note the DFC function can also be controlled by I2C access. ©2017 Integrated Device Technology, Inc. 4 October 24, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Source Selection Register Settings Table 3. OUT3 Source Table 4. OUT2 Source Table 5. OUT1 Source Table 6. DIV1 Source Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 8. OE1 Pin Function Table 9. SDA/SCL Function Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 10. Output Divider 1 Table 11. Output Dividers 2, 3, and 5 Table 12. Output Divider 4 Output Clock Test Conditions Absolute Maximum Ratings Table 13: Absolute Maximum Ratings Recommended Operating Conditions Table 14: Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 15: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Recommended Crystal Characteristics Table 16: Crystal Characteristics DC Electrical Characteristics Table 17: DC Electrical Characteristics DC Electrical Characteristics for 1.8V LVCMOS Table 18: DC Electrical Characteristics for 1.8V LVCMOS AC Electrical Characteristics Table 19. AC Electrical Characteristics I2C Bus Characteristics Table 20. I2C Bus DC Characteristics Table 21. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 22: Spread Spectrum Generation Specifications General I2C Serial Interface Information Package Drawings Figure 5. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 1 Figure 6. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 2 Marking Diagram Ordering Information Revision History