Datasheet AP3917B (Diodes) - 9

AP3917B Performance Characteristics
(continued)
Overshoot Improvement
In general, there is no capacitor between FB pin and S pin. But in some cases where strict overshoot is required, we recommend a ceramic capacitor C6 (390pF to 1nF) in Figure 5. R1 D2 C3 C2 C6 R2 L2 BP S VO+ FB S NC Drain NC AP3917B Figure 5. Overshoot Improvement
Leading-Edge Blanking
A narrow spike on the leading edge of the current waveform can usually be observed when the power MOSFET is turned on. Normally, the leading-edge blanking time tLEB1 is built in to prevent the false-triggering caused by the turn-on spike. But in the case of short circuit, the leading- edge blanking time is tLEB2. During this period, the current limit comparator is disabled, and the gate driver cannot be switched off. AP3917B 9 of 12 May 2019 Document number: DS41277 Rev. 5 - 2
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