Datasheet ADP5072 (Analog Devices) - 6

ADP5072 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 A PVIN SW2 SW1 PGND B AVIN PVIN SW1 PGND C EN2 SYNC SEQ EN1 D AGND SLEW SS FB1 E COMP2 FB2 VREF COMP1
002 12069- Figure 2. Pin Configuration (Top View)
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
A1, B2 PVIN Power Input for the Boost Regulator. A2 SW2 Switching Node for the Inverting Regulator. A3, B3 SW1 Switching Node for the Boost Regulator. A4, B4 PGND Power Ground for the Boost Regulator. B1 AVIN System Power Supply for the ADP5072. C1 EN2 Inverting Regulator Precision Enable. The EN2 pin is compared to an internal precision reference to enable the inverting regulator output. C2 SYNC Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pul the SYNC pin high. To set the switching frequency to 1.2 MHz, pull the SYNC pin low. To synchronize the switching frequency, connect the SYNC pin to an external clock. C3 SEQ Start-Up Sequence Control. For manual VPOS/VNEG startup using an individual precision enabling pin, ENx, leave the SEQ pin open. For simultaneous VPOS/VNEG startup when the EN2 pin rises, connect the SEQ pin to PVIN (the EN1 pin can be used to enable the internal references early, if required). For a sequenced startup, pull the SEQ pin low. Either EN1 or EN2 can be used, and the corresponding supply is the first in sequence. Hold the other enable pin low. C4 EN1 Boost Regulator Precision Enable. The EN1 pin is compared to an internal precision reference to enable the boost regulator output. D1 AGND Analog Ground. D2 SLEW Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the SW1 and SW2 drivers. For the fastest slew rate (optimal efficiency), leave the SLEW pin open. For normal slew rate, connect the SLEW pin to PVIN. For the slowest slew rate (optimal noise performance), connect the SLEW pin to AGND. D3 SS Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft start time, connect a resistor between the SS pin and AGND. D4 FB1 Feedback Input for the Boost Regulator. Connect a resistor divider between the positive side of the boost regulator output capacitor and AGND to program the output voltage. E1 COMP2 Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between this pin and AGND. E2 FB2 Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the inverting regulator output capacitor and VREF to program the output voltage. E3 VREF Inverting Regulator Reference Output. Connect a 1.0 µF ceramic filter capacitor between the VREF pin and AGND. E4 COMP1 Error Amplifier Compensation for the Boost Regulator. Connect the compensation network between this pin and AGND. Rev. 0 | Page 6 of 24 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PWM MODE PSM MODE UNDERVOLTAGE LOCKOUT (UVLO) OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATOR PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION THERMAL SHUTDOWN START-UP SEQUENCE APPLICATIONS INFORMATION COMPONENT SELECTION Feedback Resistors OUTPUT CAPACITORS Input Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator LOOP COMPENSATION Boost Regulator Inverting Regulator COMMON APPLICATIONS LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE