Datasheet LT3757, LT3757A (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Boost, Flyback, SEPIC and Inverting Controller |
| 页数 / 页 | 38 / 8 — BLOCK DIAGRAM. Figure 1. LT3757 Block Diagram Working as a SEPIC Converter |
| 修订版 | F |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
BLOCK DIAGRAM. Figure 1. LT3757 Block Diagram Working as a SEPIC Converter
该数据表的模型线
- LT3757AEDD#PBF LT3757AEDD#TRPBF LT3757AEMSE#PBF LT3757AEMSE#TRPBF LT3757AEMSE#WPBF LT3757AEMSE#WTRPBF LT3757AHMSE#PBF LT3757AHMSE#TRPBF LT3757AHMSE#WPBF LT3757AHMSE#WTRPBF LT3757AIDD#PBF LT3757AIDD#TRPBF LT3757AIMSE#PBF LT3757AIMSE#TRPBF LT3757AIMSE#WPBF LT3757AIMSE#WTRPBF LT3757AMPMSE#PBF LT3757AMPMSE#TRPBF LT3757EDD#PBF LT3757EDD#TRPBF LT3757EMSE#PBF LT3757EMSE#TRPBF LT3757HMSE#PBF LT3757HMSE#TRPBF LT3757IDD#PBF LT3757IDD#TRPBF LT3757IMSE#PBF LT3757IMSE#TRPBF LT3757MPMSE#PBF LT3757MPMSE#TRPBF
文件文字版本
LT3757/LT3757A
BLOCK DIAGRAM
L1 CDC D1 VIN • VOUT R4 R3 + CIN L2 C R2 OUT2 • + FBX COUT1 9 10 R1 V SHDN/UVLO IN A10 I – S1 2.5V 2µA + 1.22V I 2.5V INTERNAL S3 REGULATOR AND UVLO I CURRENT S2 V 17.5V LIMIT C 10µA UVLO + 1 A9 Q3 7.2V LDO INTV – CC CVCC G4 G3 8 A8 CC2 RC + 2.7V UP CC1 1.72V A11 – – TSD 2.6V DOWN 165˚C + DRIVER G6 SR1 A12 VC – GATE – A7 G5 R O G2 7 + M1 –0.88V + S Q2 PWM COMPARATOR – 108mV 1.6V +A1 A6 FBX – SLOPE V + ISENSE SENSE FBX 2 + RAMP + 6 A2 RAMP A5 – R –0.8V GND SENSE – GENERATOR 1.25V – 11 +A3 G1 100kHz-1MHz OSCILLATOR 1.25V FREQ + FREQUENCY FOLDBACK + FOLDBACK A4 Q1 R5 – FREQ D2 8k D3 PROG SS SYNC RT 3 5 4 3757 F01 CSS RT
Figure 1. LT3757 Block Diagram Working as a SEPIC Converter
Rev. F 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
BLOCK DIAGRAM
L1 CDC D1 VIN • VOUT R4 R3 + CIN L2 C R2 OUT2 • + FBX COUT1 9 10 R1 V SHDN/UVLO IN A10 I – S1 2.5V 2µA + 1.22V I 2.5V INTERNAL S3 REGULATOR AND UVLO I CURRENT S2 V 17.5V LIMIT C 10µA UVLO + 1 A9 Q3 7.2V LDO INTV – CC CVCC G4 G3 8 A8 CC2 RC + 2.7V UP CC1 1.72V A11 – – TSD 2.6V DOWN 165˚C + DRIVER G6 SR1 A12 VC – GATE – A7 G5 R O G2 7 + M1 –0.88V + S Q2 PWM COMPARATOR – 108mV 1.6V +A1 A6 FBX – SLOPE V + ISENSE SENSE FBX 2 + RAMP + 6 A2 RAMP A5 – R –0.8V GND SENSE – GENERATOR 1.25V – 11 +A3 G1 100kHz-1MHz OSCILLATOR 1.25V FREQ + FREQUENCY FOLDBACK + FOLDBACK A4 Q1 R5 – FREQ D2 8k D3 PROG SS SYNC RT 3 5 4 3757 F01 CSS RT
Figure 1. LT3757 Block Diagram Working as a SEPIC Converter
Rev. F 8 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts