Datasheet LTC3309A (Analog Devices) - 9

LTC3309A
PIN FUNCTIONS AGND (Pin 1):
The AGND pin is the output voltage remote
SW (Pins 5, 6):
The SW pins are the switching outputs of ground sense. Connect the AGND pin directly to the nega- the internal power switches. Connect these pins together tive terminal of the output capacitor at the load. The AGND and to the inductor with a short, wide trace. pin is also the ground reference for the internal analog
MODE/SYNC (Pin 9):
The MODE/SYNC pin is a mode circuitry. Place a small analog bypass 1nF, 0201 or 0402 selection and external clock synchronization input. Ground ceramic capacitor as close as possible to the VIN (Pin 3) this pin to enable Pulse Skip mode at light loads. For and AGND pins. Connect RT and FB returns to AGND as higher efficiency at light loads, tie this pin to V well. IN to enable the low-ripple Burst Mode operation. For faster transient
EN (Pin 2):
The EN pin has a precision IC enable thresh- response, lower noise and full frequency operation over old with hysteresis. An external resistor divider, from a wide load range, float this pin to enable forced continu- VIN or from another supply, can be used to program the ous mode. Drive MODE/SYNC with an external clock to threshold below which the LTC3309A will shut down. If synchronize the switcher to the applied frequency. While the precision threshold is not required, tie EN directly synchronizing, the part operates in the forced continuous to VIN. When the EN pin is low the LTC3309A enters a mode. The slope compensation is automatically adapted low current shutdown mode where all internal circuitry to the external clock frequency. In the absence of an is disabled. Do not float this pin. external clock the switching frequency is determined by
V
the RT pin.
IN (Pins 3, 8):
The VIN pins supply current to internal circuitry and topside power switch. Connect both VIN pins
RT (Pin 10):
The RT pin sets the switching frequency with together with short wide traces and bypass to PGND and an external resistor to AGND. If this pin is tied to VIN, the AGND with low ESR capacitors located as close as pos- buck will switch at the default oscillator frequency. If the sible to the pins. external clock is driving the MODE/SYNC pin, the RT pin
PGND (Pins 4, 7, Exposed Pad Pin 13):
The PGND pins is ignored. are the return path of the internal bottom side power
PGOOD (Pin 11):
The PGOOD pin is the open drain output switch. Connect the negative terminal of the input capaci- of an internal power good comparator. When the regulated tors as close to the PGND pins as possible. For low para- output voltage falls below the PGOOD threshold or rises sitic inductance and good thermal performance, connect above the overvoltage threshold, this pin is pul ed low. Pin 4 and Pin 7 to a large continuous ground plane on When VIN is above VIN UVLO and the part is in shutdown, the printed circuit board directly under the LTC3309A. this pin is also pulled low. The PGND exposed pad is the main electrical and thermal
FB (Pin 12):
Program the output voltage and close the highway and should be connected to large PCB ground control loop by connecting this pin to the middle node plane(s) with many vias. of a resistor divider between the VOUT and AGND. The LTC3309A regulates FB to 500mV (typical). A phase lead capacitor connected between FB and VOUT may be used to optimize transient response. Rev. 0 For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts