Datasheet LTC3310S (Analog Devices) - 10

link to page 14 link to page 14 LTC3310S
PIN FUNCTIONS EN (Pin 1):
The EN pin has a precision enable threshold
PGOOD (Pin 14):
The PGOOD pin is a power good pin and with hysteresis. An external resistor divider, from VIN or is the open drain output of an internal comparator. The from another supply, programs the threshold below which PGOOD output is pulled low when VIN is above 2.25V and the LTC3310S will shut down. If the precision threshold the part is in shutdown. is not used, directly connect the pin to VIN. When the EN
RT (Pin 15):
The RT pin sets the oscillator frequency pin is low, the LTC3310S enters a low current shutdown with an external resistor to AGND or sets the phasing mode where all internal circuitry is disabled. for multiphase operation. (see Multiphase Operation in
AGND (Pin 2):
The AGND pin is the output voltage remote Applications Information). ground sense. Connect the AGND pin directly to the nega-
SSTT (Pin 16):
Soft-Start, Track, Temperature Monitor. tive terminal of the output capacitor at the load and to the An internal 10µA current into an external capacitor on the feedback divider resistor. soft-start pin programs the output voltage ramp rate dur-
VIN (Pins 3, 4, 11, 12):
The VIN pins supply current to the ing start-up. During the soft-start cycle, the FB pin voltage internal circuitry and topside power switch. All of the VIN will track the SSTT pin voltage. When the soft-start cycle pins must be connected together with short, wide traces is complete, the tracking function is disabled, the internal and bypassed to PGND with low ESR capacitors located reference resumes control of the error amplifier and the as close as possible to the pins. SSTT pin servos to a voltage representative of junction
PGND (Pins 5, 10, 19):
The PGND pins are the return temperature. For a clean recovery from an output short path of the internal bottom side power switch. Connect circuit condition, the SSTT pin is pulled down to approxi- the PGND pins together and to the exposed pad. Connect mately 140mV above the VFB voltage and a new soft-start the negative terminal of the input capacitors as close to cycle is initiated. During shutdown and fault conditions, the PGND pins as possible. The PGND node is the main the SSTT pin is pulled to ground. thermal highway and should be connected to a large PCB
ITH (Pin 17):
The ITH pin is the compensation node for ground plane with many large vias. the output voltage regulation control loop. Compensation
SW (Pins 6–9):
The SW pins are the switching outputs of components connected to this pin are referenced to AGND. the internal power switches. Connect these pins together
FB (Pin 18):
The output voltage feedback pin is externally to the inductor with short, wide traces. connected to the output voltage via a resistive divider and
MODE/SYNC (Pin 13):
The MODE/SYNC pin facilitates is internally connected to the inverting input of the error multiphase operation and synchronization to an external amplifier. The LTC3310S regulates the FB pin to 500mV. clock. Depending on the mode of operation, the MODE/ A phase lead capacitor connected between VFB and VOUT SYNC pin either accepts an input clock pulse or outputs is used to optimize the transient response. a clock pulse at its operating frequency. (see Multiphase Operation in Applications Information). The MODE/SYNC pin also programs the mode of operation: pulse skip or forced continuous. Rev. B 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts