Datasheet CMX7146 (CML Microcircuits) - 4
| 制造商 | CML Microcircuits |
| 描述 | BPSK Wireless Data Modulator |
| 页数 / 页 | 37 / 4 — Transmit Functions. Auxiliary Functions. System Control. Figure 1 Block … |
| 文件格式/大小 | PDF / 2.1 Mb |
| 文件语言 | 英语 |
Transmit Functions. Auxiliary Functions. System Control. Figure 1 Block Diagram
该数据表的模型线
文件文字版本
BPSK Wireless Data Modulator CMX7146
Transmit Functions
Output 1 MOD 1 O/P Tx Tx GMSK/ Gaussian Modulator data Raw data GFSK Filter mode buffer modulator Output 2 MOD 2 O/P Data Modulator
Auxiliary Functions
System clock 1 SYSCLK1 GPIO 1 System clock 2 SYSCLK2 GPIO 2 GPIO Auxiliary System Clocks GPIO 3 GPIO 4 FI Configured I/O AUXDAC 1 DAC 1 Ramp profile RAM AUXDAC 2 DAC 2 MOSI AUXDAC 3 DAC 3 EPSCLK SSP/Flash/ EEPROM MISO AUXDAC 4 DAC 4 Auxiliary DACs Interface EPCSN FSO AUXADC1 Thresholds ADC 1 Averaging AUXADC 2 IRQN Thresholds MUX ADC 2 REPLY DATA AUXADC 3 Averaging C-BUS CSN Interface CMD DATA AUXADC 4 Auxiliary Multiplexed ADCs SERIAL CLK
System Control
Main clock PLL Power Registers control Bias Bias Boot Crystal Control oscillator D S S D C s 1 2 D A D K N I S E s N N V B V L L V D V E E A V A C A D D T T / T V O O L A X O O T B B X
Figure 1 Block Diagram
2019 CML Microsystems Plc Page 4 D/7146/1 Document Outline Datasheet Front Page 1 Brief Description 1.1 History 2 Signal List 3 External Components 4 PCB Layout Guidelines and Power Supply Decoupling 5 General Description 5.1 CMX7146 Features 6 Detailed Descriptions 6.1 Xtal Frequency 6.2 Host Interface 6.2.1 C-BUS Operation 6.3 Function Image Loading 6.3.1 FI Loading from Host Controller 6.3.2 FI Loading from Flash/EEPROM 6.4 Device Control 6.4.1 Device Configuration (using the Programming Register) 6.4.2 Device Configuration (using dedicated registers) 6.4.3 Interrupt Operation 6.4.4 Signal Routing 6.4.5 Loading Transmit Data 6.4.6 The Transmit Sequence 6.4.7 Other Modem Modes 6.4.8 Data Transfer 6.4.9 Raw Data Transfer 6.4.10 Pre-loading transmit data 6.4.11 Auxiliary clock rates 6.4.12 Auxiliary data 6.4.13 GPIO Pin Operation 6.4.14 Auxiliary ADC Operation 6.4.15 Auxiliary DAC / RAMDAC Operation 6.5 Digital System Clock Generators 6.5.1 System Clock Operation 6.6 Signal Level Optimisation 6.7 C-BUS Register Summary 7 CMX7146 FI-1.x Features 7.1 Modulation 7.2 Radio Interface 7.3 Transmit Performance 8 Performance Specification 8.1 Electrical Performance 8.1.1 Absolute Maximum Ratings 8.1.2 Operating Limits 8.1.3 Operating Characteristics 8.1.4 Parametric Performance 8.2 C-BUS Timing 8.3 Packaging END OF DOCUMENT
Transmit Functions
Output 1 MOD 1 O/P Tx Tx GMSK/ Gaussian Modulator data Raw data GFSK Filter mode buffer modulator Output 2 MOD 2 O/P Data Modulator
Auxiliary Functions
System clock 1 SYSCLK1 GPIO 1 System clock 2 SYSCLK2 GPIO 2 GPIO Auxiliary System Clocks GPIO 3 GPIO 4 FI Configured I/O AUXDAC 1 DAC 1 Ramp profile RAM AUXDAC 2 DAC 2 MOSI AUXDAC 3 DAC 3 EPSCLK SSP/Flash/ EEPROM MISO AUXDAC 4 DAC 4 Auxiliary DACs Interface EPCSN FSO AUXADC1 Thresholds ADC 1 Averaging AUXADC 2 IRQN Thresholds MUX ADC 2 REPLY DATA AUXADC 3 Averaging C-BUS CSN Interface CMD DATA AUXADC 4 Auxiliary Multiplexed ADCs SERIAL CLK
System Control
Main clock PLL Power Registers control Bias Bias Boot Crystal Control oscillator D S S D C s 1 2 D A D K N I S E s N N V B V L L V D V E E A V A C A D D T T / T V O O L A X O O T B B X
Figure 1 Block Diagram
2019 CML Microsystems Plc Page 4 D/7146/1 Document Outline Datasheet Front Page 1 Brief Description 1.1 History 2 Signal List 3 External Components 4 PCB Layout Guidelines and Power Supply Decoupling 5 General Description 5.1 CMX7146 Features 6 Detailed Descriptions 6.1 Xtal Frequency 6.2 Host Interface 6.2.1 C-BUS Operation 6.3 Function Image Loading 6.3.1 FI Loading from Host Controller 6.3.2 FI Loading from Flash/EEPROM 6.4 Device Control 6.4.1 Device Configuration (using the Programming Register) 6.4.2 Device Configuration (using dedicated registers) 6.4.3 Interrupt Operation 6.4.4 Signal Routing 6.4.5 Loading Transmit Data 6.4.6 The Transmit Sequence 6.4.7 Other Modem Modes 6.4.8 Data Transfer 6.4.9 Raw Data Transfer 6.4.10 Pre-loading transmit data 6.4.11 Auxiliary clock rates 6.4.12 Auxiliary data 6.4.13 GPIO Pin Operation 6.4.14 Auxiliary ADC Operation 6.4.15 Auxiliary DAC / RAMDAC Operation 6.5 Digital System Clock Generators 6.5.1 System Clock Operation 6.6 Signal Level Optimisation 6.7 C-BUS Register Summary 7 CMX7146 FI-1.x Features 7.1 Modulation 7.2 Radio Interface 7.3 Transmit Performance 8 Performance Specification 8.1 Electrical Performance 8.1.1 Absolute Maximum Ratings 8.1.2 Operating Limits 8.1.3 Operating Characteristics 8.1.4 Parametric Performance 8.2 C-BUS Timing 8.3 Packaging END OF DOCUMENT