Datasheet ADN2890 (Analog Devices) - 6

ADN2890 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DE HO H T C UT C A C L V I_O E _C _ S U D P PD RS SQ 6 5 4 3 1 1 1 1 AVCC 1 12 DRVCC PIN 2 11 OUTP ADN2890 NIN 3 TOP VIEW 10 OUTN (Not To Scale) AVEE 4 9 DRVEE 5 6 7 8 1 2 Z Z ADJ LOS CA CA HR T NOTES
004
1.THE EXPOSED PAD ON THE BOTTOM OF
0-
THE PACKAGE MUST BE CONNECTED TO THE GND PLANE WITH FILLED VIAS.
04509- Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic I/O Description
1 AVCC Power Analog Power 2 PIN Input Differential Data Input 3 NIN Input Differential Data Input 4 AVEE Power Analog Ground 5 THRADJ Input LOS Threshold Adjust Resistor 6 CAZ1 Offset Correction Loop Capacitor 7 CAZ2 Offset Correction Loop Capacitor 8 LOS Output LOS Detector Output 9 DRVEE Power Output Buffer Ground 10 OUTN Output Differential Data Output 11 OUTP Output Differential Data Output 12 DRVCC Power Output Buffer Power 13 SQUELCH Input Disable Outputs 14 RSSI_OUT Output Average Current Output 15 PD_VCC Power Power Input for RSSI Measurement 16 PD_CATHODE Output Photodiode Bias Voltage Exposed Pad Pad Power Connect to Ground Rev. B | Page 6 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION LIMAMP Input Buffer CML Output Buffer LOSS OF SIGNAL (LOS) DETECTOR RECEIVED SIGNAL STRENGTH INDICATOR (RSSI) SQUELCH MODE APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Power Supply Connections and Ground Planes PCB Layout Soldering Guidelines for Chip Scale Package OUTLINE DIMENSIONS ORDERING GUIDE NOTES