Datasheet AD8304 (Analog Devices) - 9

AD8304
To repeat the previous example: for a reference power level of voltage is applied to a processing block—essentially an analog divider 1 mW, a POPT of 3 mW would correspond to a DOPT of 10 log10(3) = that effectively puts a variable proportional to temperature 4.77 dBm, while the equivalent intercept power of 110 pW will underneath the T in Equation 10. In this same block, IREF is trans- correspond to a DZ of –69.6 dBm; now using Equation 8: formed to the much smaller current IZ, to provide the previously V = 20 mV 4 7 . 7 – ( 6 – 9 9 . ) 1 487 . V { } = (9) defined value for VLOG, that is, LOG V =V log (I I/ ) (11) which is in agreement with the result from Equation 7. LOG Y 10 PD Z Recall that VY is 200 mV/decade and IZ is 100 pA. Internally,
GENERAL STRUCTURE
this is generated first as an output current of 40 µA/decade The AD8304 addresses a wide variety of interfacing conditions (2 µA/dB) applied to an internal load resistor from VLOG to to meet the needs of fiber optic supervisory systems, and will also ACOM that is laser-trimmed to 5 kΩ ± 1%. The slope may be be useful in many nonoptical applications. These notes explain altered at this point by adding an external shunt resistor. This is the structure of this unique translinear log amp. Figure 1 is a required when using the minimum supply voltage of 3.0 V, simplified schematic showing the key elements. because the span of VLOG for the full 160 dB (eight-decade) range of IPD amounts to 8 ⫻ 0.2 V = 1.6 V, which exceeds the
VPDB
internal headroom at this node. Using a shunt of 5 kΩ, this is
VBE1 INTERCEPT AND 0.5V
reduced to 800 mV, that is, the slope becomes 5 mV/dB. In
VPDB TEMPERATURE PHOTODIODE VBE2– COMPENSATION
those applications needing a higher slope, the buffer can provide
INPUT CURRENT 296mVP (SUBTRACT AND
voltage gain. For example, to raise the output swing to 2.4 V,
DIVIDE BY T K) ~10k 200 I I REF
which can be accommodated by the rail-to-rail buffer when
PD (INTERNAL) VSUM 40 A/dec
using a 3.0 V supply, a gain of 3⫻ can be used which raises the
INPT 0.5V
slope to 15 mV/dB. Slope variations implemented in these ways
VLOG VLOG
do not affect the intercept. Keep in mind these measures to
0.6V C1
address the limitations of a small positive supply voltage will not
0.5V 5k
be needed when IPD is limited to about 1 mA maximum. They
Q1 QM Q2
can also be avoided by using a negative supply that allows V
V
LOG
R1 BE1 VBE2
to run below ground, which will be discussed later.
ACOM
Figure 1 shows how a sample of the input current is derived using
VNEG (NORMALLY GROUNDED)
a very small monitoring transistor, QM, connected in parallel with Q1. This is used to generate the photodiode bias, V Figure 1. Simplified Schematic PDB, at Pin VPDB, which varies from 0.6 V when IPD = 100 pA, and reverse-biases The photodiode current IPD is received at input Pin INPT. The the diode by 0.1 V (after subtracting the fixed 0.5 V at INPT
)
summing voltage at this node is essentially equal to that on the and rises to 2.6 V at IPD = 10 mA, for a net diode bias of 2 V. two adjacent guard pins, VSUM, due to the low offset voltage of The driver for this output is current-limited to about 20 mA. the ultralow bias J-FET op amp used to support the operation of The system is completed by the final buffer amplifier, which is the transistor Q1, which converts the current to a logarithmic essentially an uncommitted op amp with a rail-to-rail output voltage, as delineated in Equation 1. VSUM is needed to provide capability, a 10 MHz bandwidth, and good load-driving capabili- the collector-emitter bias for Q1, and is internally set to 0.5 V, ties, and may be used to implement multipole low-pass filters, using a quarter of the reference voltage of 2 V appearing on and a voltage reference for internal use in controlling the scaling, Pin VREF. but that is also made available at the 2.0 V level at Pin VREF. In conventional translinear log amps, the summing node is gener- Figure 2 shows the ideal output VLOG versus IPD. ally held at ground potential, but that condition is not readily
Bandwidth and Noise Considerations
realized in a single-supply part. To address this, the AD8304 also The response time and wide-band noise of translinear log amps supports the use of an optional negative supply voltage, VN, at are fundamentally a function of the signal current I Pin VNEG. For a V PD. The N of at least –0.5 V the summing node can bandwidth becomes progressively lower as I be connected to ground potential. Larger negative voltages may PD is reduced, largely due to the effects of junction capacitances in Q1. This is be used, with essentially no effect on scaling, up to a maximum easily understood by noting that the transconductance (g supply of 8 V between VPOS and VNEG. Note that the resistance m) of a bipolar transistor is a linear function of collector current, I at the VSUM pins is approximately 10 kΩ to ground; this voltage C, (hence, translinear), which in this case is just I is not intended as a general bias source. PD. The corre- sponding incremental emitter resistance is: The input-dependent VBE of Q1 is compared with the fixed VBE of 1 kT a second transistor, Q2, which operates at an accurate internally r = = e (12) g qI generated current, I m PD REF = 10 µA. The overall intercept is arranged to be 100,000 times smaller than I Basically, this resistance and the capacitance CJ of the transistor REF, in later parts of the signal chain. The difference between these two V generate a time constant of reCJ and thus a corresponding low-pass BE values can be written as corner frequency of: V – V = kT q / log (I /I ) (10) qI BE1 BE 2 10 PD REF f PD = 3dB 2 π (13) kTC Thus, the uncertain and temperature-dependent saturation current, j showing the proportionality of bandwidth to current. IS that appears in Equation 1, has been eliminated. Next, to eliminate the temperature variation of kT/q, this difference REV. A –9– Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS ORDERING GUIDE Typical Performance Characteristics BASIC CONCEPTS Optical Measurements Decibel Scaling GENERAL STRUCTURE Bandwidth and Noise Considerations Chip Enable USING THE AD8304 Slope and Intercept Adjustments Low Supply Slope and Intercept Adjustment Using the Adaptive Bias Changing the Voltage at the Summing Node Implementing Low-Pass Filters Operation in Comparator Modes Using a Negative Supply APPLICATIONS Summing Node at Ground and Voltage Inputs Providing Negative Outputs and Rescaling Inverting the Slope Programmable Level Comparator with Hysteresis Programmable Multidecade Current Source Characterization Setups and Methods Evaluation Board OUTLINE DIMENSIONS Revision History