Datasheet AD7711A (Analog Devices) - 2

AD7711A (AVDD = +5 V
6
5%; DVDD = +5 V
6
5%; VSS = 0 V or –5 V
6
5%; REF IN(+) = +2.5 V; –SPECIFICATIONS REF IN(–) = AGND; MCLK IN = 10 MHz, unless otherwise stated. All specifications TMIN to TMAX, unless otherwise noted.) Parameter A, S Versions1 Unit Conditions/Comments
STATIC PERFORMANCE No Missing Codes 24 Bits min Guaranteed by Design. For Filter Notches £ 60 Hz 22 Bits min For Filter Notch = 100 Hz 18 Bits min For Filter Notch = 250 Hz 15 Bits min For Filter Notch = 500 Hz 12 Bits min For Filter Notch = 1 kHz Output Noise See Tables I and II Depends on Filter Cutoffs and Selected Gain Integral Nonlinearity @ 25rC ± 0.0015 % FSR max Filter Notches £ 60 Hz TMIN to TMAX 0.003 % FSR max Typically ± 0.0003% Positive Full-Scale Error2, 3, 4 Excluding Reference Full-Scale Drift5 1 mV/rC typ Excluding Reference. For Gains of 1, 2 0.3 mV/rC typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128 Unipolar Offset Error2, 4 Unipolar Offset Drift5 0.5 mV/rC typ For Gains of 1, 2 0.25 mV/rC typ For Gains of 4, 8, 16, 32, 64, 128 Bipolar Zero Error2, 4 Bipolar Zero Drift5 0.5 mV/rC typ For Gains of 1, 2 0.25 mV/rC typ For Gains of 4, 8, 16, 32, 64, 128 Gain Drift 2 ppm/rC typ Bipolar Negative Full-Scale Error2 @ 25rC ± 0.003 % FSR max Excluding Reference ± 0.006 % FSR max Typically ± 0.0006% Bipolar Negative Full-Scale Drift5 1 mV/rC typ Excluding Reference. For Gains of 1, 2 TMIN to TMAX 0.3 mV/rC typ Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128 ANALOG INPUTS/REFERENCE INPUTS Common-Mode Rejection (CMR) 100 dB min At dc and AVDD = 5 V 90 dB min At dc and AVDD = 10 V Common-Mode Voltage Range6 VSS to AVDD V min to V max Normal-Mode 50 Hz Rejection7 100 dB min For Filter Notches of 10, 25, 50 Hz, ± 0.02 ¥ fNOTCH Normal-Mode 60 Hz Rejection7 100 dB min For Filter Notches of 10, 30, 60 Hz, ± 0.02 ¥ fNOTCH Common-Mode 50 Hz Rejection7 150 dB min For Filter Notches of 10, 25, 50 Hz, ± 0.02 ¥ fNOTCH Common-Mode 60 Hz Rejection7 150 dB min For Filter Notches of 10, 30, 60 Hz, ± 0.02 ¥ fNOTCH DC Input Leakage Current7 @ 25rC 10 pA max TMIN to TMAX 1 nA max Sampling Capacitance7 20 pF max Analog Inputs8 Input Voltage Range9 For Normal Operation. Depends on Gain Selected 0 to +V 10 REF nom Unipolar Input Range (B/U Bit of Control Register = 1) ± VREF nom Bipolar Input Range (B/U Bit of Control Register = 0) Input Sampling Rate, fS See Table III Reference Inputs REF IN(+) – REF IN(–) Voltage11 2.5 to 5 V min to V max For Specified Performance. Part Functions with Lower VREF Voltages Input Sampling Rate, fS fCLK IN/256 REFERENCE OUTPUT Output Voltage 2.5 V nom Initial Tolerance @ 25rC ± 1 % max Drift 20 ppm/rC typ Output Noise 30 mV typ pk-pk Noise 0.1 Hz to 10 Hz Bandwidth Line Regulation (AVDD) 1 mV/V max Load Regulation 1.5 mV/mA max Maximum Load Current 1 mA External Current 1 mA max NOTES 1Temperature ranges are as follows: A Version, –40rC to +85rC; S Version, –55rC to +125rC. 2Applies after calibration at the temperature of interest. 3Positive full-scale error applies to both unipolar and bipolar input ranges. 4These errors will be of the order of the output noise of the part as shown in Table I when using system calibration. These errors are 20 mV typical when using self- calibration or background calibration. 5Recalibration at any temperature or use of the background calibration mode will remove these drift errors. 6This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN(–) does not exceed AV DD + 30 mV and VSS – 30 mV. 7These numbers are guaranteed by design and/or characterization. 8The analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended source resistance depends on the selected gain (see Tables IV and V). 9The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The absolute voltage on the analog inputs should not go more positive than AV DD + 30 mV or go more negative than VSS – 30 mV. 10VREF = REF IN(+) – REF IN(–). 11The reference input voltage range may be restricted by the input voltage range requirement on the VBIAS input. –2– REV. D